From patchwork Fri Jun 28 02:47:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Haijun.Zhang" X-Patchwork-Id: 255266 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BD8302C0368 for ; Fri, 28 Jun 2013 13:36:06 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A69914A139; Fri, 28 Jun 2013 05:36:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id T39rrVCyFNht; Fri, 28 Jun 2013 05:36:02 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 41BFC4A124; Fri, 28 Jun 2013 05:36:00 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9B3224A124 for ; Fri, 28 Jun 2013 05:35:52 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id io5XRytUJNXt for ; Fri, 28 Jun 2013 05:35:46 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from db8outboundpool.messaging.microsoft.com (mail-db8lp0189.outbound.messaging.microsoft.com [213.199.154.189]) by theia.denx.de (Postfix) with ESMTPS id 29D9E4A11F for ; Fri, 28 Jun 2013 05:35:39 +0200 (CEST) Received: from mail120-db8-R.bigfish.com (10.174.8.243) by DB8EHSOBE020.bigfish.com (10.174.4.83) with Microsoft SMTP Server id 14.1.225.23; Fri, 28 Jun 2013 03:35:38 +0000 Received: from mail120-db8 (localhost [127.0.0.1]) by mail120-db8-R.bigfish.com (Postfix) with ESMTP id 45A12E004D for ; Fri, 28 Jun 2013 03:35:38 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: -1 X-BigFish: VS-1(zz154dIzz1f42h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ah1fc6hzz8275bhz2dh2a8h668h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1155h) Received: from mail120-db8 (localhost.localdomain [127.0.0.1]) by mail120-db8 (MessageSwitch) id 1372390535734346_20052; Fri, 28 Jun 2013 03:35:35 +0000 (UTC) Received: from DB8EHSMHS026.bigfish.com (unknown [10.174.8.229]) by mail120-db8.bigfish.com (Postfix) with ESMTP id AE1084A0046 for ; Fri, 28 Jun 2013 03:35:35 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS026.bigfish.com (10.174.4.36) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 28 Jun 2013 03:35:35 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.328.11; Fri, 28 Jun 2013 03:35:34 +0000 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r5S3ZQn8031173; Thu, 27 Jun 2013 20:35:28 -0700 From: Haijun.Zhang To: Date: Fri, 28 Jun 2013 10:47:09 +0800 Message-ID: <1372387629-10792-1-git-send-email-Haijun.Zhang@freescale.com> X-Mailer: git-send-email 1.8.0 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: Huang , Jerry@theia.denx.de, u-boot@lists.denx.de, Scott Wood , Sun Yusong-R58495 , "Haijun.Zhang" Subject: [U-Boot] [PATCH V2] p1020rdb-pd: platform support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: "Haijun.Zhang" Add new board p1020RDB-PD. P1020RDB-PD board was update from P1020RDB. DDR changed from DDR2 1G to DDR3 2G. NAND: 128 MiB Flash: 64 MiB Also change P1020RDB to P1020RDB-PC to distinguish from P1020RDB board. Signed-off-by: Jerry Huang Signed-off-by: Haijun Zhang CC: Scott Wood CC: Sun Yusong-R58495 --- changes for V2: - Add change log and update the config name for pc board board/freescale/p1_p2_rdb_pc/README | 1 + board/freescale/p1_p2_rdb_pc/ddr.c | 4 +-- board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- boards.cfg | 20 +++++++++------ include/configs/p1_p2_rdb_pc.h | 50 ++++++++++++++++++++++++++++++++++--- 5 files changed, 63 insertions(+), 14 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README index 4437731..f4cc43f 100644 --- a/board/freescale/p1_p2_rdb_pc/README +++ b/board/freescale/p1_p2_rdb_pc/README @@ -3,6 +3,7 @@ Overview P1_P2_RDB_PC represents a set of boards including P1020MSBG-PC P1020RDB-PC + P1020RDB-PD P1020UTM-PC P1021RDB-PC P1024RDB diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 9355536..c8fde72 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -80,7 +80,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tFAW_ps = 30000, }; -#elif defined(CONFIG_P1020MBG) +#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) /* Micron MT41J512M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 2, @@ -111,7 +111,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tFAW_ps = 37500, }; -#elif defined(CONFIG_P1020RDB) +#elif defined(CONFIG_P1020RDB_PC) /* * Samsung K4B2G0846C-HCF8 * The following timing are for "downshift" diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 3e4dffd..e19002f 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -110,7 +110,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), -#ifdef CONFIG_P1020MBG +#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD) /* 2G DDR on P1020MBG, map the second 1G */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, diff --git a/boards.cfg b/boards.cfg index 35f38f3..8f50927 100644 --- a/boards.cfg +++ b/boards.cfg @@ -758,16 +758,20 @@ P1020RDB_36BIT powerpc mpc85xx p1_p2_rdb freesca P1020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SDCARD P1020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SPIFLASH P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND -P1020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB -P1020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT -P1020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,NAND -P1020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,SDCARD -P1020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,SPIFLASH -P1020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,NAND -P1020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,SDCARD -P1020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,SPIFLASH +P1020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC +P1020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT +P1020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND +P1020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD +P1020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH +P1020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,NAND +P1020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,SDCARD +P1020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH +P1020RDB-PD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD +P1020RDB-PD_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD,NAND +P1020RDB-PD_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD,SDCARD +P1020RDB-PD_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH P1020UTM-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM P1020UTM-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT P1020UTM-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 964bfcd..5e804e4 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -50,7 +50,7 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020RDB) +#if defined(CONFIG_P1020RDB_PC) #define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P1020 @@ -66,6 +66,35 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif +/* + * P1020RDB-PD board has user selectable switches for evaluating different + * frequency and boot options for the P1020 device. The table that + * follow describe the available options. The front six binary number was in + * accordance with SW3[1:6]. + * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off + * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off + * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off + * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off + * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off + * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off + * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off + */ +#if defined(CONFIG_P1020RDB_PD) +#define CONFIG_BOARDNAME "P1020RDB-PD" +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_P1020 +#define CONFIG_SPI_FLASH +#define CONFIG_VSC7385_ENET +#define CONFIG_SLIC +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0x64 +#define __SW_BOOT_SPI 0x34 +#define __SW_BOOT_SD 0x24 +#define __SW_BOOT_NAND 0x44 +#define __SW_BOOT_PCIE 0x74 +#define CONFIG_SYS_L2_SIZE (256 << 10) +#endif + #if defined(CONFIG_P1021RDB) #define CONFIG_BOARDNAME "P1021RDB-PC" #define CONFIG_NAND_FSL_ELBC @@ -274,7 +303,7 @@ #define SPD_EEPROM_ADDRESS 0x52 #undef CONFIG_FSL_DDR_INTERACTIVE -#ifdef CONFIG_P1020MBG +#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #define CONFIG_CHIP_SELECTS_PER_CTRL 2 #else @@ -345,7 +374,7 @@ /* * Local Bus Definitions */ -#if defined(CONFIG_P1020MBG) +#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ #define CONFIG_SYS_FLASH_BASE 0xec000000 #elif defined(CONFIG_P1020UTM) @@ -396,13 +425,27 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND +#if defined(CONFIG_P1020RDB_PD) +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#else #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) +#endif #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<