Patchwork [U-Boot,v3,06/11] powerpc/T4240EMU: Add T4240EMU target

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Submitter York Sun
Date June 27, 2013, 5:48 p.m.
Message ID <1372355309-10864-1-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/255114/
State Accepted
Delegated to: Andy Fleming
Headers show

Comments

York Sun - June 27, 2013, 5:48 p.m.
Add emulator support for T4240. Emulator has limited peripherals and
interfaces. Difference between emulator and T4240QDS includes:
	ECC for DDR is disabled due the procedure to load images
	No board FPGA (QIXIS)
	NOR flash has 32-bit port for higher loading speed
	IFC and I2C timing don't really matter, so set them fast
	No ethernet

Signed-off-by: York Sun <yorksun@freescale.com>
---
Change since v2:
 Fixt entry in MAINTAINERS, _sorted_
Change since v1:
 Added entry to MAINTAINERS
 Fixed checkpatch warning

 MAINTAINERS                      |    4 +
 board/freescale/t4qds/Makefile   |    3 +-
 board/freescale/t4qds/ddr.c      |   73 +---
 board/freescale/t4qds/ddr.h      |  122 ++++++
 board/freescale/t4qds/law.c      |    2 +
 board/freescale/t4qds/t4240emu.c |   96 +++++
 board/freescale/t4qds/t4240qds.c |  854 ++++++++++++++++++++++++++++++++++++++
 board/freescale/t4qds/t4qds.c    |  853 -------------------------------------
 board/freescale/t4qds/tlb.c      |    3 +-
 boards.cfg                       |    1 +
 include/configs/T4240EMU.h       |  185 +++++++++
 include/configs/T4240QDS.h       |  539 ++++++++++++++++++++++++
 include/configs/t4qds.h          |  482 +--------------------
 13 files changed, 1810 insertions(+), 1407 deletions(-)
 create mode 100644 board/freescale/t4qds/ddr.h
 create mode 100644 board/freescale/t4qds/t4240emu.c
 create mode 100644 board/freescale/t4qds/t4240qds.c
 delete mode 100644 board/freescale/t4qds/t4qds.c
 create mode 100644 include/configs/T4240EMU.h

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 7820375..94b1922 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -471,6 +471,10 @@  Ira W. Snyder <iws@ovro.caltech.edu>
 
 	P2020COME	P2020
 
+York Sun <yorksun@freescale.com>
+
+	T4240EMU	T4240
+
 Timur Tabi <timur@freescale.com>
 
 	MPC8349E-mITX	MPC8349
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index ff09ffa..1923a47 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -24,7 +24,8 @@  include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS-y	+= $(BOARD).o
+COBJS-$(CONFIG_T4240QDS) += t4240qds.o
+COBJS-$(CONFIG_T4240EMU) += t4240emu.o
 COBJS-y	+= ddr.o
 COBJS-$(CONFIG_T4240QDS)+= eth.o
 COBJS-$(CONFIG_PCI)	+= pci.o
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 058d625..26ac2a5 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -13,81 +13,10 @@ 
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 rank_gb;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2T;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
-	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
-	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-	{}
-};
-
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x07080805,   0xff,    2,  0},
-	{4,  1666, 0, 5,     8, 0x08070605, 0x07080805,   0xff,    2,  0},
-	{4,  2140, 0, 5,     8, 0x08070605, 0x07081805,   0xff,    2,  0},
-	{2,  1350, 0, 5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{2,  2140, 0, 5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-	{}
-};
-
-/*
- * The three slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
-	rdimm0,
-};
-
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
new file mode 100644
index 0000000..cde0785
--- /dev/null
+++ b/board/freescale/t4qds/ddr.h
@@ -0,0 +1,122 @@ 
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+#ifdef CONFIG_T4240QDS
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
+	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+	{4,  1350, 0, 5,     9, 0x08070605, 0x07080805,   0xff,    2,  0},
+	{4,  1666, 0, 5,     8, 0x08070605, 0x07080805,   0xff,    2,  0},
+	{4,  2140, 0, 5,     8, 0x08070605, 0x07081805,   0xff,    2,  0},
+	{2,  1350, 0, 5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1666, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{2,  2140, 0, 5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{}
+};
+
+#else	/* CONFIG_T4240EMU */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+	{2,  2140, 0, 4,     8, 0x0, 0x0,   0xff,    2,  0},
+	{1,  2140, 0, 4,     8, 0x0, 0x0,   0xff,    2,  0},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+	{4,  2140, 0, 5,     8, 0x0, 0x0,   0xff,    2,  0},
+	{2,  2140, 0, 5,     8, 0x0, 0x0,   0xff,    2,  0},
+	{1,  2140, 0, 4,     8, 0x0, 0x0,   0xff,    2,  0},
+	{}
+};
+#endif	/* CONFIG_T4240EMU */
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+};
+
+
+#endif
diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
index f3848f3..7e41556 100644
--- a/board/freescale/t4qds/law.c
+++ b/board/freescale/t4qds/law.c
@@ -35,7 +35,9 @@  struct law_entry law_table[] = {
 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
 	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
+#ifdef QIXIS_BASE_PHYS
 	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
new file mode 100644
index 0000000..589a2ae
--- /dev/null
+++ b/board/freescale/t4qds/t4240emu.c
@@ -0,0 +1,96 @@ 
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	struct cpu_type *cpu = gd->arch.cpu;
+
+	printf("Board: %sEMU\n", cpu->name);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	fdt_fixup_liodn(blob);
+	fdt_fixup_dr_usb(blob, bd);
+}
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
new file mode 100644
index 0000000..89e56a3
--- /dev/null
+++ b/board/freescale/t4qds/t4240qds.c
@@ -0,0 +1,854 @@ 
+/*
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "t4qds.h"
+#include "t4240qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+				{8, 8}, {9, 9}, {14, 14}, {15, 15} };
+
+static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+				{10, 10}, {11, 11}, {12, 12}, {13, 13} };
+
+static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+				{10, 11}, {11, 10}, {12, 2}, {13, 3} };
+
+static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+				{8, 9}, {9, 8}, {14, 1}, {15, 0} };
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+	struct cpu_type *cpu = gd->arch.cpu;
+	unsigned int i;
+
+	printf("Board: %sQDS, ", cpu->name);
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+	       QIXIS_READ(id), QIXIS_READ(arch));
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("Promjet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+	printf("FPGA: v%d (%s), build %d",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+
+	/*
+	 * Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES Reference Clocks: ");
+	sw = QIXIS_READ(brdcfg[2]);
+	for (i = 0; i < MAX_SERDES; i++) {
+		static const char * const freq[] = {
+			"100", "125", "156.25", "161.1328125"};
+		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
+
+		printf("SERDES%u=%sMHz ", i+1, freq[clock]);
+	}
+	puts("\n");
+
+	return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for 532us befor another reading
+ */
+#define NUM_READINGS	4	/* prefer to be power of 2 for efficiency */
+#define WAIT_FOR_ADC	532	/* wait for 532 microseconds for ADC */
+
+static inline int read_voltage(void)
+{
+	int i, ret, voltage_read = 0;
+	u16 vol_mon;
+
+	for (i = 0; i < NUM_READINGS; i++) {
+		ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+			I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
+		if (ret) {
+			printf("VID: failed to read core voltage\n");
+			return ret;
+		}
+		if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+			printf("VID: Core voltage sensor error\n");
+			return -1;
+		}
+		debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+		/* LSB = 4mv */
+		voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+		udelay(WAIT_FOR_ADC);
+	}
+	/* calculate the average */
+	voltage_read /= NUM_READINGS;
+
+	return voltage_read;
+}
+
+/*
+ * We need to calculate how long before the voltage starts to drop or increase
+ * It returns with the loop count. Each loop takes several readings (532us)
+ */
+static inline int wait_for_voltage_change(int vdd_last)
+{
+	int timeout, vdd_current;
+
+	vdd_current = read_voltage();
+	/* wait until voltage starts to drop */
+	for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
+		timeout < 100; timeout++) {
+		vdd_current = read_voltage();
+	}
+	if (timeout >= 100) {
+		printf("VID: Voltage adjustment timeout\n");
+		return -1;
+	}
+	return timeout;
+}
+
+/*
+ * argument 'wait' is the time we know the voltage difference can be measured
+ * this function keeps reading the voltage until it is stable
+ */
+static inline int wait_for_voltage_stable(int wait)
+{
+	int timeout, vdd_current, vdd_last;
+
+	vdd_last = read_voltage();
+	udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
+	/* wait until voltage is stable */
+	vdd_current = read_voltage();
+	for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
+		timeout < 100; timeout++) {
+		vdd_last = vdd_current;
+		udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
+		vdd_current = read_voltage();
+	}
+	if (timeout >= 100) {
+		printf("VID: Voltage adjustment timeout\n");
+		return -1;
+	}
+
+	return vdd_current;
+}
+
+static inline int set_voltage(u8 vid)
+{
+	int wait, vdd_last;
+
+	vdd_last = read_voltage();
+	QIXIS_WRITE(brdcfg[6], vid);
+	wait = wait_for_voltage_change(vdd_last);
+	if (wait < 0)
+		return -1;
+	debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
+	wait = wait ? wait : 1;
+
+	vdd_last = wait_for_voltage_stable(wait);
+	if (vdd_last < 0)
+		return -1;
+	debug("VID: Current voltage is %d mV\n", vdd_last);
+
+	return vdd_last;
+}
+
+
+static int adjust_vdd(ulong vdd_override)
+{
+	int re_enable = disable_interrupts();
+	ccsr_gur_t __iomem *gur =
+		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 fusesr;
+	u8 vid, vid_current;
+	int vdd_target, vdd_current, vdd_last;
+	int ret;
+	unsigned long vdd_string_override;
+	char *vdd_string;
+	static const uint16_t vdd[32] = {
+		0,	/* unused */
+		9875,	/* 0.9875V */
+		9750,
+		9625,
+		9500,
+		9375,
+		9250,
+		9125,
+		9000,
+		8875,
+		8750,
+		8625,
+		8500,
+		8375,
+		8250,
+		8125,
+		10000,	/* 1.0000V */
+		10125,
+		10250,
+		10375,
+		10500,
+		10625,
+		10750,
+		10875,
+		11000,
+		0,	/* reserved */
+	};
+	struct vdd_drive {
+		u8 vid;
+		unsigned voltage;
+	};
+
+	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
+	if (ret) {
+		debug("VID: I2c failed to switch channel\n");
+		ret = -1;
+		goto exit;
+	}
+
+	/* get the voltage ID from fuse status register */
+	fusesr = in_be32(&gur->dcfg_fusesr);
+	vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+		FSL_CORENET_DCFG_FUSESR_VID_MASK;
+	if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
+		vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+			FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+	}
+	vdd_target = vdd[vid];
+
+	/* check override variable for overriding VDD */
+	vdd_string = getenv("t4240qds_vdd_mv");
+	if (vdd_override == 0 && vdd_string &&
+	    !strict_strtoul(vdd_string, 10, &vdd_string_override))
+		vdd_override = vdd_string_override;
+	if (vdd_override >= 819 && vdd_override <= 1212) {
+		vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+		debug("VDD override is %lu\n", vdd_override);
+	} else if (vdd_override != 0) {
+		printf("Invalid value.\n");
+	}
+
+	if (vdd_target == 0) {
+		debug("VID: VID not used\n");
+		ret = 0;
+		goto exit;
+	} else {
+		/* round up and divice by 10 to get a value in mV */
+		vdd_target = DIV_ROUND_UP(vdd_target, 10);
+		debug("VID: vid = %d mV\n", vdd_target);
+	}
+
+	/*
+	 * Check current board VID setting
+	 * Voltage regulator support output to 6.250mv step
+	 * The highes voltage allowed for this board is (vid=0x40) 1.21250V
+	 * the lowest is (vid=0x7f) 0.81875V
+	 */
+	vid_current =  QIXIS_READ(brdcfg[6]);
+	vdd_current = 121250 - (vid_current - 0x40) * 625;
+	debug("VID: Current vid setting is (0x%x) %d mV\n",
+	      vid_current, vdd_current/100);
+
+	/*
+	 * Read voltage monitor to check real voltage.
+	 * Voltage monitor LSB is 4mv.
+	 */
+	vdd_last = read_voltage();
+	if (vdd_last < 0) {
+		printf("VID: Could not read voltage sensor abort VID adjustment\n");
+		ret = -1;
+		goto exit;
+	}
+	debug("VID: Core voltage is at %d mV\n", vdd_last);
+	/*
+	 * Adjust voltage to at or 8mV above target.
+	 * Each step of adjustment is 6.25mV.
+	 * Stepping down too fast may cause over current.
+	 */
+	while (vdd_last > 0 && vid_current < 0x80 &&
+		vdd_last > (vdd_target + 8)) {
+		vid_current++;
+		vdd_last = set_voltage(vid_current);
+	}
+	/*
+	 * Check if we need to step up
+	 * This happens when board voltage switch was set too low
+	 */
+	while (vdd_last > 0 && vid_current >= 0x40 &&
+		vdd_last < vdd_target + 2) {
+		vid_current--;
+		vdd_last = set_voltage(vid_current);
+	}
+	if (vdd_last > 0)
+		printf("VID: Core voltage %d mV\n", vdd_last);
+	else
+		ret = -1;
+
+exit:
+	if (re_enable)
+		enable_interrupts();
+	return ret;
+}
+
+/* Configure Crossbar switches for Front-Side SerDes Ports */
+int config_frontside_crossbar_vsc3316(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s1, srds_prtcl_s2;
+	int ret;
+
+	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
+	if (ret)
+		return ret;
+
+	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+	if (srds_prtcl_s1) {
+		ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
+		if (ret)
+			return ret;
+		ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
+		if (ret)
+			return ret;
+	}
+
+	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	if (srds_prtcl_s2) {
+		ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
+		if (ret)
+			return ret;
+		ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int config_backside_crossbar_mux(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s3, srds_prtcl_s4;
+	u8 brdcfg;
+
+	srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
+	srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
+	switch (srds_prtcl_s3) {
+	case 0:
+		/* SerDes3 is not enabled */
+		break;
+	case 2:
+	case 9:
+	case 10:
+		/* SD3(0:7) => SLOT5(0:7) */
+		brdcfg = QIXIS_READ(brdcfg[12]);
+		brdcfg &= ~BRDCFG12_SD3MX_MASK;
+		brdcfg |= BRDCFG12_SD3MX_SLOT5;
+		QIXIS_WRITE(brdcfg[12], brdcfg);
+		break;
+	case 4:
+	case 6:
+	case 8:
+	case 12:
+	case 14:
+	case 16:
+	case 17:
+	case 19:
+	case 20:
+		/* SD3(4:7) => SLOT6(0:3) */
+		brdcfg = QIXIS_READ(brdcfg[12]);
+		brdcfg &= ~BRDCFG12_SD3MX_MASK;
+		brdcfg |= BRDCFG12_SD3MX_SLOT6;
+		QIXIS_WRITE(brdcfg[12], brdcfg);
+		break;
+	default:
+		printf("WARNING: unsupported for SerDes3 Protocol %d\n",
+		       srds_prtcl_s3);
+		return -1;
+	}
+
+	srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
+	srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
+	switch (srds_prtcl_s4) {
+	case 0:
+		/* SerDes4 is not enabled */
+		break;
+	case 2:
+		/* 10b, SD4(0:7) => SLOT7(0:7) */
+		brdcfg = QIXIS_READ(brdcfg[12]);
+		brdcfg &= ~BRDCFG12_SD4MX_MASK;
+		brdcfg |= BRDCFG12_SD4MX_SLOT7;
+		QIXIS_WRITE(brdcfg[12], brdcfg);
+		break;
+	case 4:
+	case 6:
+	case 8:
+		/* x1b, SD4(4:7) => SLOT8(0:3) */
+		brdcfg = QIXIS_READ(brdcfg[12]);
+		brdcfg &= ~BRDCFG12_SD4MX_MASK;
+		brdcfg |= BRDCFG12_SD4MX_SLOT8;
+		QIXIS_WRITE(brdcfg[12], brdcfg);
+		break;
+	case 10:
+	case 12:
+	case 14:
+	case 16:
+	case 18:
+		/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
+		brdcfg = QIXIS_READ(brdcfg[12]);
+		brdcfg &= ~BRDCFG12_SD4MX_MASK;
+		brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
+		QIXIS_WRITE(brdcfg[12], brdcfg);
+		break;
+	default:
+		printf("WARNING: unsupported for SerDes4 Protocol %d\n",
+		       srds_prtcl_s4);
+		return -1;
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+
+	/* Disable remote I2C connection to qixis fpga */
+	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
+
+	/*
+	 * Adjust core voltage according to voltage ID
+	 * This function changes I2C mux to channel 2.
+	 */
+	if (adjust_vdd(0))
+		printf("Warning: Adjusting core voltage failed.\n");
+
+	/* Configure board SERDES ports crossbar */
+	config_frontside_crossbar_vsc3316();
+	config_backside_crossbar_mux();
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+	/* use accurate clock measurement */
+	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
+	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+	u32 val;
+
+	val =  freq * base;
+	if (val) {
+		debug("SYS Clock measurement is: %d\n", val);
+		return val;
+	} else {
+		printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
+	}
+#endif
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+	/* use accurate clock measurement */
+	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
+	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+	u32 val;
+
+	val =  freq * base;
+	if (val) {
+		debug("DDR Clock measurement is: %d\n", val);
+		return val;
+	} else {
+		printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
+	}
+#endif
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	case SRDS_PLLCR0_RFCK_SEL_161_13:
+		return "161.1328125";
+	default:
+		return "???";
+	}
+}
+
+int misc_init_r(void)
+{
+	u8 sw;
+	serdes_corenet_t *srds_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 actual[MAX_SERDES];
+	unsigned int i;
+
+	sw = QIXIS_READ(brdcfg[2]);
+	for (i = 0; i < MAX_SERDES; i++) {
+		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
+		switch (clock) {
+		case 0:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+			break;
+		case 1:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+			break;
+		case 2:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+			break;
+		case 3:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
+			break;
+		}
+	}
+
+	for (i = 0; i < MAX_SERDES; i++) {
+		u32 pllcr0 = srds_regs->bank[i].pllcr0;
+		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (expected != actual[i]) {
+			printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
+			       i + 1, serdes_clock_to_string(expected),
+			       serdes_clock_to_string(actual[i]));
+		}
+	}
+
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+}
+
+/*
+ * This function is called by bdinfo to print detail board information.
+ * As an exmaple for future board, we organize the messages into
+ * several sections. If applicable, the message is in the format of
+ * <name>      = <value>
+ * It should aligned with normal output of bdinfo command.
+ *
+ * Voltage: Core, DDR and another configurable voltages
+ * Clock  : Critical clocks which are not printed already
+ * RCW    : RCW source if not printed already
+ * Misc   : Other important information not in above catagories
+ */
+void board_detail(void)
+{
+	int i;
+	u8 brdcfg[16], dutcfg[16], rst_ctl;
+	int vdd, rcwsrc;
+	static const char * const clk[] = {"66.67", "100", "125", "133.33"};
+
+	for (i = 0; i < 16; i++) {
+		brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+		dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+	}
+
+	/* Voltage secion */
+	if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
+		vdd = read_voltage();
+		if (vdd > 0)
+			printf("Core voltage= %d mV\n", vdd);
+		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	}
+
+	printf("XVDD        = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
+
+	/* clock section */
+	printf("SYSCLK      = %s MHz\nDDRCLK      = %s MHz\n",
+	       clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
+
+	/* RCW section */
+	rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
+	puts("RCW source  = ");
+	switch (rcwsrc) {
+	case 0x017:
+	case 0x01f:
+		puts("8-bit NOR\n");
+		break;
+	case 0x027:
+	case 0x02F:
+		puts("16-bit NOR\n");
+		break;
+	case 0x040:
+		puts("SDHC/eMMC\n");
+		break;
+	case 0x044:
+		puts("SPI 16-bit addressing\n");
+		break;
+	case 0x045:
+		puts("SPI 24-bit addressing\n");
+		break;
+	case 0x048:
+		puts("I2C normal addressing\n");
+		break;
+	case 0x049:
+		puts("I2C extended addressing\n");
+		break;
+	case 0x108:
+	case 0x109:
+	case 0x10a:
+	case 0x10b:
+		puts("8-bit NAND, 2KB\n");
+		break;
+	default:
+		if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
+			puts("Hard-coded RCW\n");
+		else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
+			puts("8-bit NAND, 4KB\n");
+		else
+			puts("unknown\n");
+		break;
+	}
+
+	/* Misc section */
+	rst_ctl = QIXIS_READ(rst_ctl);
+	puts("HRESET_REQ  = ");
+	switch (rst_ctl & 0x30) {
+	case 0x00:
+		puts("Ignored\n");
+		break;
+	case 0x10:
+		puts("Assert HRESET\n");
+		break;
+	case 0x30:
+		puts("Reset system\n");
+		break;
+	default:
+		puts("N/A\n");
+		break;
+	}
+}
+
+/*
+ * Reverse engineering switch settings.
+ * Some bits cannot be figured out. They will be displayed as
+ * underscore in binary format. mask[] has those bits.
+ * Some bits are calculated differently than the actual switches
+ * if booting with overriding by FPGA.
+ */
+void qixis_dump_switch(void)
+{
+	int i;
+	u8 sw[9];
+
+	/*
+	 * Any bit with 1 means that bit cannot be reverse engineered.
+	 * It will be displayed as _ in binary format.
+	 */
+	static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
+	char buf[10];
+	u8 brdcfg[16], dutcfg[16];
+
+	for (i = 0; i < 16; i++) {
+		brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+		dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+	}
+
+	sw[0] = dutcfg[0];
+	sw[1] = (dutcfg[1] << 0x07)		|
+		((dutcfg[12] & 0xC0) >> 1)	|
+		((dutcfg[11] & 0xE0) >> 3)	|
+		((dutcfg[6] & 0x80) >> 6)	|
+		((dutcfg[1] & 0x80) >> 7);
+	sw[2] = ((brdcfg[1] & 0x0f) << 4)	|
+		((brdcfg[1] & 0x30) >> 2)	|
+		((brdcfg[1] & 0x40) >> 5)	|
+		((brdcfg[1] & 0x80) >> 7);
+	sw[3] = brdcfg[2];
+	sw[4] = ((dutcfg[2] & 0x01) << 7)	|
+		((dutcfg[2] & 0x06) << 4)	|
+		((~QIXIS_READ(present)) & 0x10)	|
+		((brdcfg[3] & 0x80) >> 4)	|
+		((brdcfg[3] & 0x01) << 2)	|
+		((brdcfg[6] == 0x62) ? 3 :
+		((brdcfg[6] == 0x5a) ? 2 :
+		((brdcfg[6] == 0x5e) ? 1 : 0)));
+	sw[5] = ((brdcfg[0] & 0x0f) << 4)	|
+		((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
+		((brdcfg[0] & 0x40) >> 5);
+	sw[6] = (brdcfg[11] & 0x20)		|
+		((brdcfg[5] & 0x02) << 3);
+	sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
+		((brdcfg[5] & 0x10) << 2);
+	sw[8] = ((brdcfg[12] & 0x08) << 4)	|
+		((brdcfg[12] & 0x03) << 5);
+
+	puts("DIP switch (reverse-engineering)\n");
+	for (i = 0; i < 9; i++) {
+		printf("SW%d         = 0b%s (0x%02x)\n",
+		       i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
+	}
+}
+
+static int do_vdd_adjust(cmd_tbl_t *cmdtp,
+			 int flag, int argc,
+			 char * const argv[])
+{
+	ulong override;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	if (!strict_strtoul(argv[1], 10, &override))
+		adjust_vdd(override);	/* the value is checked by callee */
+	else
+		return CMD_RET_USAGE;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	vdd_override, 2, 0, do_vdd_adjust,
+	"Override VDD",
+	"- override with the voltage specified in mV, eg. 1050"
+);
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
deleted file mode 100644
index 67de0ea..0000000
--- a/board/freescale/t4qds/t4qds.c
+++ /dev/null
@@ -1,853 +0,0 @@ 
-/*
- * Copyright 2009-2012 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-
-#include "../common/qixis.h"
-#include "../common/vsc3316_3308.h"
-#include "t4qds.h"
-#include "t4240qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
-				{8, 8}, {9, 9}, {14, 14}, {15, 15} };
-
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
-				{10, 10}, {11, 11}, {12, 12}, {13, 13} };
-
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
-				{10, 11}, {11, 10}, {12, 2}, {13, 3} };
-
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
-				{8, 9}, {9, 8}, {14, 1}, {15, 0} };
-
-int checkboard(void)
-{
-	char buf[64];
-	u8 sw;
-	struct cpu_type *cpu = gd->arch.cpu;
-	unsigned int i;
-
-	printf("Board: %sQDS, ", cpu->name);
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
-		QIXIS_READ(id), QIXIS_READ(arch));
-
-	sw = QIXIS_READ(brdcfg[0]);
-	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
-	if (sw < 0x8)
-		printf("vBank: %d\n", sw);
-	else if (sw == 0x8)
-		puts("Promjet\n");
-	else if (sw == 0x9)
-		puts("NAND\n");
-	else
-		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
-	printf("FPGA: v%d (%s), build %d",
-		(int)QIXIS_READ(scver), qixis_read_tag(buf),
-		(int)qixis_read_minor());
-	/* the timestamp string contains "\n" at the end */
-	printf(" on %s", qixis_read_time(buf));
-
-	/*
-	 * Display the actual SERDES reference clocks as configured by the
-	 * dip switches on the board.  Note that the SWx registers could
-	 * technically be set to force the reference clocks to match the
-	 * values that the SERDES expects (or vice versa).  For now, however,
-	 * we just display both values and hope the user notices when they
-	 * don't match.
-	 */
-	puts("SERDES Reference Clocks: ");
-	sw = QIXIS_READ(brdcfg[2]);
-	for (i = 0; i < MAX_SERDES; i++) {
-		static const char *freq[] = {
-			"100", "125", "156.25", "161.1328125"};
-		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
-
-		printf("SERDES%u=%sMHz ", i+1, freq[clock]);
-	}
-	puts("\n");
-
-	return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch)
-{
-	int ret;
-
-	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-	if (ret) {
-		puts("PCA: failed to select proper channel\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-/*
- * read_voltage from sensor on I2C bus
- * We use average of 4 readings, waiting for 532us befor another reading
- */
-#define NUM_READINGS	4	/* prefer to be power of 2 for efficiency */
-#define WAIT_FOR_ADC	532	/* wait for 532 microseconds for ADC */
-
-static inline int read_voltage(void)
-{
-	int i, ret, voltage_read = 0;
-	u16 vol_mon;
-
-	for (i = 0; i < NUM_READINGS; i++) {
-		ret = i2c_read(I2C_VOL_MONITOR_ADDR,
-			I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
-		if (ret) {
-			printf("VID: failed to read core voltage\n");
-			return ret;
-		}
-		if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
-			printf("VID: Core voltage sensor error\n");
-			return -1;
-		}
-		debug("VID: bus voltage reads 0x%04x\n", vol_mon);
-		/* LSB = 4mv */
-		voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
-		udelay(WAIT_FOR_ADC);
-	}
-	/* calculate the average */
-	voltage_read /= NUM_READINGS;
-
-	return voltage_read;
-}
-
-/*
- * We need to calculate how long before the voltage starts to drop or increase
- * It returns with the loop count. Each loop takes several readings (532us)
- */
-static inline int wait_for_voltage_change(int vdd_last)
-{
-	int timeout, vdd_current;
-
-	vdd_current = read_voltage();
-	/* wait until voltage starts to drop */
-	for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
-		timeout < 100; timeout++) {
-		vdd_current = read_voltage();
-	}
-	if (timeout >= 100) {
-		printf("VID: Voltage adjustment timeout\n");
-		return -1;
-	}
-	return timeout;
-}
-
-/*
- * argument 'wait' is the time we know the voltage difference can be measured
- * this function keeps reading the voltage until it is stable
- */
-static inline int wait_for_voltage_stable(int wait)
-{
-	int timeout, vdd_current, vdd_last;
-
-	vdd_last = read_voltage();
-	udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
-	/* wait until voltage is stable */
-	vdd_current = read_voltage();
-	for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
-		timeout < 100; timeout++) {
-		vdd_last = vdd_current;
-		udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
-		vdd_current = read_voltage();
-	}
-	if (timeout >= 100) {
-		printf("VID: Voltage adjustment timeout\n");
-		return -1;
-	}
-
-	return vdd_current;
-}
-
-static inline int set_voltage(u8 vid)
-{
-	int wait, vdd_last;
-
-	vdd_last = read_voltage();
-	QIXIS_WRITE(brdcfg[6], vid);
-	wait = wait_for_voltage_change(vdd_last);
-	if (wait < 0)
-		return -1;
-	debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
-	wait = wait ? wait : 1;
-
-	vdd_last = wait_for_voltage_stable(wait);
-	if (vdd_last < 0)
-		return -1;
-	debug("VID: Current voltage is %d mV\n", vdd_last);
-
-	return vdd_last;
-}
-
-
-static int adjust_vdd(ulong vdd_override)
-{
-	int re_enable = disable_interrupts();
-	ccsr_gur_t __iomem *gur =
-		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 fusesr;
-	u8 vid, vid_current;
-	int vdd_target, vdd_current, vdd_last;
-	int ret;
-	unsigned long vdd_string_override;
-	char *vdd_string;
-	static const uint16_t vdd[32] = {
-		0,	/* unused */
-		9875,	/* 0.9875V */
-		9750,
-		9625,
-		9500,
-		9375,
-		9250,
-		9125,
-		9000,
-		8875,
-		8750,
-		8625,
-		8500,
-		8375,
-		8250,
-		8125,
-		10000,	/* 1.0000V */
-		10125,
-		10250,
-		10375,
-		10500,
-		10625,
-		10750,
-		10875,
-		11000,
-		0,	/* reserved */
-	};
-	struct vdd_drive {
-		u8 vid;
-		unsigned voltage;
-	};
-
-	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
-	if (ret) {
-		debug("VID: I2c failed to switch channel\n");
-		ret = -1;
-		goto exit;
-	}
-
-	/* get the voltage ID from fuse status register */
-	fusesr = in_be32(&gur->dcfg_fusesr);
-	vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
-		FSL_CORENET_DCFG_FUSESR_VID_MASK;
-	if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
-		vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
-			FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
-	}
-	vdd_target = vdd[vid];
-
-	/* check override variable for overriding VDD */
-	vdd_string = getenv("t4240qds_vdd_mv");
-	if (vdd_override == 0 && vdd_string &&
-	    !strict_strtoul(vdd_string, 10, &vdd_string_override))
-		vdd_override = vdd_string_override;
-	if (vdd_override >= 819 && vdd_override <= 1212) {
-		vdd_target = vdd_override * 10; /* convert to 1/10 mV */
-		debug("VDD override is %lu\n", vdd_override);
-	} else if (vdd_override != 0) {
-		printf("Invalid value.\n");
-	}
-
-	if (vdd_target == 0) {
-		debug("VID: VID not used\n");
-		ret = 0;
-		goto exit;
-	} else {
-		/* round up and divice by 10 to get a value in mV */
-		vdd_target = DIV_ROUND_UP(vdd_target, 10);
-		debug("VID: vid = %d mV\n", vdd_target);
-	}
-
-	/*
-	 * Check current board VID setting
-	 * Voltage regulator support output to 6.250mv step
-	 * The highes voltage allowed for this board is (vid=0x40) 1.21250V
-	 * the lowest is (vid=0x7f) 0.81875V
-	 */
-	vid_current =  QIXIS_READ(brdcfg[6]);
-	vdd_current = 121250 - (vid_current - 0x40) * 625;
-	debug("VID: Current vid setting is (0x%x) %d mV\n",
-	      vid_current, vdd_current/100);
-
-	/*
-	 * Read voltage monitor to check real voltage.
-	 * Voltage monitor LSB is 4mv.
-	 */
-	vdd_last = read_voltage();
-	if (vdd_last < 0) {
-		printf("VID: Could not read voltage sensor abort VID adjustment\n");
-		ret = -1;
-		goto exit;
-	}
-	debug("VID: Core voltage is at %d mV\n", vdd_last);
-	/*
-	 * Adjust voltage to at or 8mV above target.
-	 * Each step of adjustment is 6.25mV.
-	 * Stepping down too fast may cause over current.
-	 */
-	while (vdd_last > 0 && vid_current < 0x80 &&
-		vdd_last > (vdd_target + 8)) {
-		vid_current++;
-		vdd_last = set_voltage(vid_current);
-	}
-	/*
-	 * Check if we need to step up
-	 * This happens when board voltage switch was set too low
-	 */
-	while (vdd_last > 0 && vid_current >= 0x40 &&
-		vdd_last < vdd_target + 2) {
-		vid_current--;
-		vdd_last = set_voltage(vid_current);
-	}
-	if (vdd_last > 0)
-		printf("VID: Core voltage %d mV\n", vdd_last);
-	else
-		ret = -1;
-
-exit:
-	if (re_enable)
-		enable_interrupts();
-	return ret;
-}
-
-/* Configure Crossbar switches for Front-Side SerDes Ports */
-int config_frontside_crossbar_vsc3316(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_prtcl_s1, srds_prtcl_s2;
-	int ret;
-
-	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
-	if (ret)
-		return ret;
-
-	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	if (srds_prtcl_s1) {
-		ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
-		if (ret)
-			return ret;
-		ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
-		if (ret)
-			return ret;
-	}
-
-	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	if (srds_prtcl_s2) {
-		ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
-		if (ret)
-			return ret;
-		ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-int config_backside_crossbar_mux(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_prtcl_s3, srds_prtcl_s4;
-	u8 brdcfg;
-
-	srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
-	srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
-	switch (srds_prtcl_s3) {
-	case 0:
-		/* SerDes3 is not enabled */
-		break;
-	case 2:
-	case 9:
-	case 10:
-		/* SD3(0:7) => SLOT5(0:7) */
-		brdcfg = QIXIS_READ(brdcfg[12]);
-		brdcfg &= ~BRDCFG12_SD3MX_MASK;
-		brdcfg |= BRDCFG12_SD3MX_SLOT5;
-		QIXIS_WRITE(brdcfg[12], brdcfg);
-		break;
-	case 4:
-	case 6:
-	case 8:
-	case 12:
-	case 14:
-	case 16:
-	case 17:
-	case 19:
-	case 20:
-		/* SD3(4:7) => SLOT6(0:3) */
-		brdcfg = QIXIS_READ(brdcfg[12]);
-		brdcfg &= ~BRDCFG12_SD3MX_MASK;
-		brdcfg |= BRDCFG12_SD3MX_SLOT6;
-		QIXIS_WRITE(brdcfg[12], brdcfg);
-		break;
-	default:
-		printf("WARNING: unsupported for SerDes3 Protocol %d\n",
-				srds_prtcl_s3);
-		return -1;
-	}
-
-	srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
-	srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
-	switch (srds_prtcl_s4) {
-	case 0:
-		/* SerDes4 is not enabled */
-		break;
-	case 2:
-		/* 10b, SD4(0:7) => SLOT7(0:7) */
-		brdcfg = QIXIS_READ(brdcfg[12]);
-		brdcfg &= ~BRDCFG12_SD4MX_MASK;
-		brdcfg |= BRDCFG12_SD4MX_SLOT7;
-		QIXIS_WRITE(brdcfg[12], brdcfg);
-		break;
-	case 4:
-	case 6:
-	case 8:
-		/* x1b, SD4(4:7) => SLOT8(0:3) */
-		brdcfg = QIXIS_READ(brdcfg[12]);
-		brdcfg &= ~BRDCFG12_SD4MX_MASK;
-		brdcfg |= BRDCFG12_SD4MX_SLOT8;
-		QIXIS_WRITE(brdcfg[12], brdcfg);
-		break;
-	case 10:
-	case 12:
-	case 14:
-	case 16:
-	case 18:
-		/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
-		brdcfg = QIXIS_READ(brdcfg[12]);
-		brdcfg &= ~BRDCFG12_SD4MX_MASK;
-		brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
-		QIXIS_WRITE(brdcfg[12], brdcfg);
-		break;
-	default:
-		printf("WARNING: unsupported for SerDes4 Protocol %d\n",
-				srds_prtcl_s4);
-		return -1;
-	}
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* invalidate existing TLB entry for flash + promjet */
-	disable_tlb(flash_esel);
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
-	setup_portals();
-#endif
-
-	/* Disable remote I2C connection to qixis fpga */
-	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
-
-	/*
-	 * Adjust core voltage according to voltage ID
-	 * This function changes I2C mux to channel 2.
-	 */
-	if (adjust_vdd(0))
-		printf("Warning: Adjusting core voltage failed.\n");
-
-	/* Configure board SERDES ports crossbar */
-	config_frontside_crossbar_vsc3316();
-	config_backside_crossbar_mux();
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
-	/* use accurate clock measurement */
-	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
-	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
-	u32 val;
-
-	val =  freq * base;
-	if (val) {
-		debug("SYS Clock measurement is: %d\n", val);
-		return val;
-	} else {
-		printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
-	}
-#endif
-
-	switch (sysclk_conf & 0x0F) {
-	case QIXIS_SYSCLK_83:
-		return 83333333;
-	case QIXIS_SYSCLK_100:
-		return 100000000;
-	case QIXIS_SYSCLK_125:
-		return 125000000;
-	case QIXIS_SYSCLK_133:
-		return 133333333;
-	case QIXIS_SYSCLK_150:
-		return 150000000;
-	case QIXIS_SYSCLK_160:
-		return 160000000;
-	case QIXIS_SYSCLK_166:
-		return 166666666;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
-	/* use accurate clock measurement */
-	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
-	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
-	u32 val;
-
-	val =  freq * base;
-	if (val) {
-		debug("DDR Clock measurement is: %d\n", val);
-		return val;
-	} else {
-		printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
-	}
-#endif
-
-	switch ((ddrclk_conf & 0x30) >> 4) {
-	case QIXIS_DDRCLK_100:
-		return 100000000;
-	case QIXIS_DDRCLK_125:
-		return 125000000;
-	case QIXIS_DDRCLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-static const char *serdes_clock_to_string(u32 clock)
-{
-	switch (clock) {
-	case SRDS_PLLCR0_RFCK_SEL_100:
-		return "100";
-	case SRDS_PLLCR0_RFCK_SEL_125:
-		return "125";
-	case SRDS_PLLCR0_RFCK_SEL_156_25:
-		return "156.25";
-	case SRDS_PLLCR0_RFCK_SEL_161_13:
-		return "161.1328125";
-	default:
-		return "???";
-	}
-}
-
-int misc_init_r(void)
-{
-	u8 sw;
-	serdes_corenet_t *srds_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	u32 actual[MAX_SERDES];
-	unsigned int i;
-
-	sw = QIXIS_READ(brdcfg[2]);
-	for (i = 0; i < MAX_SERDES; i++) {
-		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
-		switch (clock) {
-		case 0:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
-			break;
-		case 1:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
-			break;
-		case 2:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
-			break;
-		case 3:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
-			break;
-		}
-	}
-
-	for (i = 0; i < MAX_SERDES; i++) {
-		u32 pllcr0 = srds_regs->bank[i].pllcr0;
-		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
-		if (expected != actual[i]) {
-			printf("Warning: SERDES%u expects reference clock"
-			       " %sMHz, but actual is %sMHz\n", i + 1,
-			       serdes_clock_to_string(expected),
-			       serdes_clock_to_string(actual[i]));
-		}
-	}
-
-	return 0;
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = getenv_bootm_low();
-	size = getenv_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-	fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-	fdt_fixup_fman_ethernet(blob);
-	fdt_fixup_board_enet(blob);
-#endif
-}
-
-/*
- * This function is called by bdinfo to print detail board information.
- * As an exmaple for future board, we organize the messages into
- * several sections. If applicable, the message is in the format of
- * <name>      = <value>
- * It should aligned with normal output of bdinfo command.
- *
- * Voltage: Core, DDR and another configurable voltages
- * Clock  : Critical clocks which are not printed already
- * RCW    : RCW source if not printed already
- * Misc   : Other important information not in above catagories
- */
-void board_detail(void)
-{
-	int i;
-	u8 brdcfg[16], dutcfg[16], rst_ctl;
-	int vdd, rcwsrc;
-	static const char * const clk[] = {"66.67", "100", "125", "133.33"};
-
-	for (i = 0; i < 16; i++) {
-		brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
-		dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
-	}
-
-	/* Voltage secion */
-	if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
-		vdd = read_voltage();
-		if (vdd > 0)
-			printf("Core voltage= %d mV\n", vdd);
-		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	}
-
-	printf("XVDD        = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
-
-	/* clock section */
-	printf("SYSCLK      = %s MHz\nDDRCLK      = %s MHz\n",
-	       clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
-
-	/* RCW section */
-	rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
-	puts("RCW source  = ");
-	switch (rcwsrc) {
-	case 0x017:
-	case 0x01f:
-		puts("8-bit NOR\n");
-		break;
-	case 0x027:
-	case 0x02F:
-		puts("16-bit NOR\n");
-		break;
-	case 0x040:
-		puts("SDHC/eMMC\n");
-		break;
-	case 0x044:
-		puts("SPI 16-bit addressing\n");
-		break;
-	case 0x045:
-		puts("SPI 24-bit addressing\n");
-		break;
-	case 0x048:
-		puts("I2C normal addressing\n");
-		break;
-	case 0x049:
-		puts("I2C extended addressing\n");
-		break;
-	case 0x108:
-	case 0x109:
-	case 0x10a:
-	case 0x10b:
-		puts("8-bit NAND, 2KB\n");
-		break;
-	default:
-		if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
-			puts("Hard-coded RCW\n");
-		else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
-			puts("8-bit NAND, 4KB\n");
-		else
-			puts("unknown\n");
-		break;
-	}
-
-	/* Misc section */
-	rst_ctl = QIXIS_READ(rst_ctl);
-	puts("HRESET_REQ  = ");
-	switch (rst_ctl & 0x30) {
-	case 0x00:
-		puts("Ignored\n");
-		break;
-	case 0x10:
-		puts("Assert HRESET\n");
-		break;
-	case 0x30:
-		puts("Reset system\n");
-		break;
-	default:
-		puts("N/A\n");
-		break;
-	}
-}
-
-/*
- * Reverse engineering switch settings.
- * Some bits cannot be figured out. They will be displayed as
- * underscore in binary format. mask[] has those bits.
- * Some bits are calculated differently than the actual switches
- * if booting with overriding by FPGA.
- */
-void qixis_dump_switch(void)
-{
-	int i;
-	u8 sw[9];
-
-	/*
-	 * Any bit with 1 means that bit cannot be reverse engineered.
-	 * It will be displayed as _ in binary format.
-	 */
-	static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
-	char buf[10];
-	u8 brdcfg[16], dutcfg[16];
-
-	for (i = 0; i < 16; i++) {
-		brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
-		dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
-	}
-
-	sw[0] = dutcfg[0];
-	sw[1] = (dutcfg[1] << 0x07)		| \
-		((dutcfg[12] & 0xC0) >> 1)	| \
-		((dutcfg[11] & 0xE0) >> 3)	| \
-		((dutcfg[6] & 0x80) >> 6)	| \
-		((dutcfg[1] & 0x80) >> 7);
-	sw[2] = ((brdcfg[1] & 0x0f) << 4)	| \
-		((brdcfg[1] & 0x30) >> 2)	| \
-		((brdcfg[1] & 0x40) >> 5)	| \
-		((brdcfg[1] & 0x80) >> 7);
-	sw[3] = brdcfg[2];
-	sw[4] = ((dutcfg[2] & 0x01) << 7)	| \
-		((dutcfg[2] & 0x06) << 4)	| \
-		((~QIXIS_READ(present)) & 0x10)	| \
-		((brdcfg[3] & 0x80) >> 4)	| \
-		((brdcfg[3] & 0x01) << 2)	| \
-		((brdcfg[6] == 0x62) ? 3 :	\
-		((brdcfg[6] == 0x5a) ? 2 :	\
-		((brdcfg[6] == 0x5e) ? 1 : 0)));
-	sw[5] = ((brdcfg[0] & 0x0f) << 4)	| \
-		((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
-		((brdcfg[0] & 0x40) >> 5);
-	sw[6] = (brdcfg[11] & 0x20)		|
-		((brdcfg[5] & 0x02) << 3);
-	sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
-		((brdcfg[5] & 0x10) << 2);
-	sw[8] = ((brdcfg[12] & 0x08) << 4)	| \
-		((brdcfg[12] & 0x03) << 5);
-
-	puts("DIP switch (reverse-engineering)\n");
-	for (i = 0; i < 9; i++) {
-		printf("SW%d         = 0b%s (0x%02x)\n",
-			i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
-	}
-}
-
-static int do_vdd_adjust(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong override;
-
-	if (argc < 2)
-		return CMD_RET_USAGE;
-	if (!strict_strtoul(argv[1], 10, &override))
-		adjust_vdd(override);	/* the value is checked by callee */
-	else
-		return CMD_RET_USAGE;
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	vdd_override, 2, 0, do_vdd_adjust,
-	"Override VDD",
-	"- override with the voltage specified in mV, eg. 1050"
-);
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 92c01cf..08bf1f0 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -127,10 +127,11 @@  struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
+#ifdef QIXIS_BASE_PHYS
 	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 17, BOOKE_PAGESZ_4K, 1),
-
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 1e598cb..6a1d56b 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -910,6 +910,7 @@  stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M
 T4240QDS                     powerpc     mpc85xx     t4qds               freescale      -           T4240QDS:PPC_T4240
+T4240EMU                     powerpc     mpc85xx     t4qds               freescale	-           T4240EMU:PPC_T4240
 T4240QDS_SDCARD              powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 T4240QDS_SPIFLASH            powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 T4160QDS                     powerpc     mpc85xx     t4qds               freescale      -           T4240QDS:PPC_T4160
diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h
new file mode 100644
index 0000000..399e878
--- /dev/null
+++ b/include/configs/T4240EMU.h
@@ -0,0 +1,185 @@ 
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * T4240 EMU board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_T4240EMU
+#define CONFIG_PHYS_64BIT
+
+#define CONFIG_SYS_NO_FLASH		1
+#define CONFIG_SYS_FSL_DDR_EMU		1
+#define CONFIG_SYS_FSL_NO_QIXIS		1
+#define CONFIG_SYS_FSL_NO_SERDES	1
+
+#include "t4qds.h"
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CACHE_FLUSH
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE         0x2000
+
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133333333
+#define CONFIG_FSL_TBCLK_EXTRA_DIV 100
+
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM	1
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
+#define SPD_EEPROM_ADDRESS4	0x54
+#define SPD_EEPROM_ADDRESS5	0x55
+#define SPD_EEPROM_ADDRESS6	0x56
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_32 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(0)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+				FTIM0_NOR_TEADC(0x1) | \
+				FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+				FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
+				FTIM2_NOR_TCH(0x0) | \
+				FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+
+/* I2C */
+#define CONFIG_SYS_I2C_SPEED		4000000	/* faster speed for emulator */
+
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	50
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	50
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_INTERLAKEN
+
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+
+
+#define CONFIG_BOOTDELAY	0
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t4240emu/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t4240emu/t4240emu.dtb\0"				\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the proof point
+ * app code automatically
+ */
+#define CONFIG_PROOF_POINTS			\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x29000000 - - -;"		\
+	"cpu 2 release 0x29000000 - - -;"		\
+	"cpu 3 release 0x29000000 - - -;"		\
+	"cpu 4 release 0x29000000 - - -;"		\
+	"cpu 5 release 0x29000000 - - -;"		\
+	"cpu 6 release 0x29000000 - - -;"		\
+	"cpu 7 release 0x29000000 - - -;"		\
+	"go 0x29000000"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_LINUX					\
+	"errata;"					\
+	"setenv othbootargs ignore_loglevel;"		\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 6dd5c0d..6294f2b 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -23,6 +23,9 @@ 
 /*
  * T4240 QDS board configuration file
  */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
 #define CONFIG_T4240QDS
 #define CONFIG_PHYS_64BIT
 
@@ -31,4 +34,540 @@ 
 
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
 
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
+#endif
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_DDR_ECC
+
 #include "t4qds.h"
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
+#define SPD_EEPROM_ADDRESS4	0x54
+#define SPD_EEPROM_ADDRESS5	0x55
+#define SPD_EEPROM_ADDRESS6	0x56
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE			0xffdf0000
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x83
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/* I2C */
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */
+
+#define I2C_MUX_CH_DEFAULT	0x8
+#define I2C_MUX_CH_VOL_MONITOR	0xa
+#define I2C_MUX_CH_VSC3316_FS	0xc
+#define I2C_MUX_CH_VSC3316_BS	0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR		0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
+#define VSC3316_FSM_TX_ADDR	0x70
+#define VSC3316_FSM_RX_ADDR	0x71
+
+/*
+ * RapidIO
+ */
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	50
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	50
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#define FM1_10GEC1_PHY_ADDR	0x0
+#define FM1_10GEC2_PHY_ADDR	0x1
+#define FM2_10GEC1_PHY_ADDR	0x2
+#define FM2_10GEC2_PHY_ADDR	0x3
+#endif
+
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+
+#define __USB_PHY_TYPE	utmi
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t4240qds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t4240qds/t4240qds.dtb\0"				\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x01000000 - - -;"		\
+	"cpu 2 release 0x01000000 - - -;"		\
+	"cpu 3 release 0x01000000 - - -;"		\
+	"cpu 4 release 0x01000000 - - -;"		\
+	"cpu 5 release 0x01000000 - - -;"		\
+	"cpu 6 release 0x01000000 - - -;"		\
+	"cpu 7 release 0x01000000 - - -;"		\
+	"go 0x01000000"
+
+#define CONFIG_LINUX				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 3f7b82d..c3fa3b7 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -23,15 +23,8 @@ 
 /*
  * Corenet DS style board configuration file
  */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
-#endif
+#ifndef __T4QDS_H
+#define __T4QDS_H
 
 #define CONFIG_CMD_REGINFO
 
@@ -69,63 +62,12 @@ 
 
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#else
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#endif
-
-#ifndef CONFIG_SYS_NO_FLASH
-#if defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_BUS              0
-#define CONFIG_ENV_SPI_CS               0
-#define CONFIG_ENV_SPI_MAX_HZ           10000000
-#define CONFIG_ENV_SPI_MODE             0
-#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
-#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
-#define CONFIG_ENV_SECT_SIZE            0x10000
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV          0
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_OFFSET		(512 * 1097)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
-#endif
-#else /* CONFIG_SYS_NO_FLASH */
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
-#endif
-
-
-
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BTB			/* toggle branch predition */
-#define	CONFIG_DDR_ECC
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
@@ -149,13 +91,6 @@  unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
 
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM	0
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-
 /*
  * DDR Setup
  */
@@ -171,15 +106,6 @@  unsigned long get_board_ddr_clk(void);
 #define CONFIG_DDR_SPD
 #define CONFIG_FSL_DDR3
 
-#define CONFIG_SYS_SPD_BUS_NUM	0
-#define SPD_EEPROM_ADDRESS1	0x51
-#define SPD_EEPROM_ADDRESS2	0x52
-#define SPD_EEPROM_ADDRESS3	0x53
-#define SPD_EEPROM_ADDRESS4	0x54
-#define SPD_EEPROM_ADDRESS5	0x55
-#define SPD_EEPROM_ADDRESS6	0x56
-#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 
 /*
  * IFC Definitions
@@ -187,171 +113,9 @@  unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FLASH_BASE	0xe0000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
-				+ 0x8000000) | \
-				CSPR_PORT_SIZE_16 | \
-				CSPR_MSEL_NOR | \
-				CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
-				CSPR_PORT_SIZE_16 | \
-				CSPR_MSEL_NOR | \
-				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
-
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
-				FTIM0_NOR_TEADC(0x5) | \
-				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
-				FTIM1_NOR_TRAD_NOR(0x1A) |\
-				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
-				FTIM2_NOR_TCH(0x4) | \
-				FTIM2_NOR_TWPH(0x0E) | \
-				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
-					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
-#define QIXIS_BASE			0xffdf0000
-#define QIXIS_LBMAP_SWITCH		6
-#define QIXIS_LBMAP_MASK		0x0f
-#define QIXIS_LBMAP_SHIFT		0
-#define QIXIS_LBMAP_DFLTBANK		0x00
-#define QIXIS_LBMAP_ALTBANK		0x04
-#define QIXIS_RST_CTL_RESET		0x83
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
-#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
-
-#define CONFIG_SYS_CSPR3_EXT	(0xf)
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8 \
-				| CSPR_MSEL_GPCM \
-				| CSPR_V)
-#define CONFIG_SYS_AMASK3	IFC_AMASK(4 * 1024)
-#define CONFIG_SYS_CSOR3	0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
-					FTIM0_GPCM_TEADC(0x0e) | \
-					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
-					FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
-					FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3		0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
-				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
-				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
-				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
-				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
-				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
-				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
-				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
-				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
-					FTIM0_NAND_TWP(0x18)   | \
-					FTIM0_NAND_TWCHT(0x07) | \
-					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
-					FTIM1_NAND_TWBE(0x39)  | \
-					FTIM1_NAND_TRR(0x0e)   | \
-					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
-					FTIM2_NAND_TREH(0x0a) | \
-					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW		11
-
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-
-#if defined(CONFIG_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
-#endif
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 
@@ -412,28 +176,9 @@  unsigned long get_board_ddr_clk(void);
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_OFFSET		0x118000
 #define CONFIG_SYS_I2C2_OFFSET		0x118100
-#define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */
-
-#define I2C_MUX_CH_DEFAULT	0x8
-#define I2C_MUX_CH_VOL_MONITOR	0xa
-#define I2C_MUX_CH_VSC3316_FS	0xc
-#define I2C_MUX_CH_VSC3316_BS	0xd
-
-/* Voltage monitor on channel 2*/
-#define I2C_VOL_MONITOR_ADDR		0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
-
-/* VSC Crossbar switches */
-#define CONFIG_VSC_CROSSBAR
-#define VSC3316_FSM_TX_ADDR	0x70
-#define VSC3316_FSM_RX_ADDR	0x71
 
 /*
  * RapidIO
@@ -447,44 +192,6 @@  unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 
 /*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED         10000000
-#define CONFIG_SF_DEFAULT_MODE          0
-
-/*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
@@ -527,66 +234,6 @@  unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS	50
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_NUM_PORTALS	50
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_INTERLAKEN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
- */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
-#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_TERANETICS
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#define FM1_10GEC1_PHY_ADDR	0x0
-#define FM1_10GEC2_PHY_ADDR	0x1
-#define FM2_10GEC1_PHY_ADDR	0x2
-#define FM2_10GEC2_PHY_ADDR	0x3
-#endif
-
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_NET_MULTI
@@ -649,30 +296,6 @@  unsigned long get_board_ddr_clk(void);
 #endif
 
 /*
-* USB
-*/
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
-#define CONFIG_HAS_FSL_DR_USB
-
-#define CONFIG_MMC
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
@@ -713,112 +336,11 @@  unsigned long get_board_ddr_clk(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
-#define __USB_PHY_TYPE	utmi
-
-/*
- * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be
- * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to
- * cacheline interleaving. It can be cacheline, page, bank, superbank.
- * See doc/README.fsl-ddr for details.
- */
-#ifdef CONFIG_PPC_T4240
-#define CTRL_INTLV_PREFERED 3way_4KB
-#else
-#define CTRL_INTLV_PREFERED cacheline
-#endif
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"hwconfig=fsl_ddr:"					\
-	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
-	"bank_intlv=auto;"					\
-	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
-	"netdev=eth0\0"						\
-	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
-	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
-	"tftpflash=tftpboot $loadaddr $uboot && "		\
-	"protect off $ubootaddr +$filesize && "			\
-	"erase $ubootaddr +$filesize && "			\
-	"cp.b $loadaddr $ubootaddr $filesize && "		\
-	"protect on $ubootaddr +$filesize && "			\
-	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
-	"consoledev=ttyS0\0"					\
-	"ramdiskaddr=2000000\0"					\
-	"ramdiskfile=t4240qds/ramdisk.uboot\0"			\
-	"fdtaddr=c00000\0"					\
-	"fdtfile=t4240qds/t4240qds.dtb\0"				\
-	"bdev=sda3\0"						\
-	"c=ffe\0"
-
-/* For emulation this causes u-boot to jump to the start of the proof point
-   app code automatically */
-#define CONFIG_PROOF_POINTS			\
- "setenv bootargs root=/dev/$bdev rw "		\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "cpu 1 release 0x29000000 - - -;"		\
- "cpu 2 release 0x29000000 - - -;"		\
- "cpu 3 release 0x29000000 - - -;"		\
- "cpu 4 release 0x29000000 - - -;"		\
- "cpu 5 release 0x29000000 - - -;"		\
- "cpu 6 release 0x29000000 - - -;"		\
- "cpu 7 release 0x29000000 - - -;"		\
- "go 0x29000000"
-
 #define CONFIG_HVBOOT				\
  "setenv bootargs config-addr=0x60000000; "	\
  "bootm 0x01000000 - 0x00f00000"
 
-#define CONFIG_ALU				\
- "setenv bootargs root=/dev/$bdev rw "		\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "cpu 1 release 0x01000000 - - -;"		\
- "cpu 2 release 0x01000000 - - -;"		\
- "cpu 3 release 0x01000000 - - -;"		\
- "cpu 4 release 0x01000000 - - -;"		\
- "cpu 5 release 0x01000000 - - -;"		\
- "cpu 6 release 0x01000000 - - -;"		\
- "cpu 7 release 0x01000000 - - -;"		\
- "go 0x01000000"
-
-#define CONFIG_LINUX				\
- "setenv bootargs root=/dev/ram rw "		\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "setenv ramdiskaddr 0x02000000;"		\
- "setenv fdtaddr 0x00c00000;"			\
- "setenv loadaddr 0x1000000;"			\
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT					\
-	"setenv bootargs root=/dev/$bdev rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $loadaddr $bootfile;"			\
-	"tftp $fdtaddr $fdtfile;"			\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND			\
-	"setenv bootargs root=/dev/nfs rw "	\
-	"nfsroot=$serverip:$rootpath "		\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $loadaddr $bootfile;"		\
-	"tftp $fdtaddr $fdtfile;"		\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND				\
-	"setenv bootargs root=/dev/ram rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $ramdiskaddr $ramdiskfile;"		\
-	"tftp $loadaddr $bootfile;"			\
-	"tftp $fdtaddr $fdtfile;"			\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
-
-#ifdef CONFIG_SECURE_BOOT
-#include <asm/fsl_secure_boot.h>
-#endif
-
 #endif	/* __CONFIG_H */