From patchwork Thu Jun 27 13:26:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin Liang See X-Patchwork-Id: 255081 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5030D2C0082 for ; Thu, 27 Jun 2013 23:43:49 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 21FDE4A025; Thu, 27 Jun 2013 15:43:19 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gd516xdK7cWx; Thu, 27 Jun 2013 15:43:18 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 63BBD4A027; Thu, 27 Jun 2013 15:43:00 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B188F4A01F for ; Thu, 27 Jun 2013 15:38:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Dju6MUJtwFF3 for ; Thu, 27 Jun 2013 15:38:03 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ie0-f196.google.com (mail-ie0-f196.google.com [209.85.223.196]) by theia.denx.de (Postfix) with ESMTPS id 957BE4A01C for ; Thu, 27 Jun 2013 15:37:58 +0200 (CEST) Received: by mail-ie0-f196.google.com with SMTP id x12so559994ief.3 for ; Thu, 27 Jun 2013 06:37:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=dCFtqfRtfBiscvqKwlWA1sl1cEbpq3slHvDSUrS46Dg=; b=E5v3efSjuWjSRhEs5a2d0P5I1x3xGHw/yxhnLfec7PltvZVIjH2FSdixRiL5MTX2sM KfFcCV5UEOKFg4iP2Mod6aIOwkeqq5K77YtGeCXzTL/69kIjHXniE+8UW95tUp1fu3+7 WTtNgI1Md5Hycvx4Wbz8gW+NejJSqMV019yUOP3xTubtbLYDnR0DPLFlBSrGOtU6mTi4 28XkCJcLYomcsKePTs+FWUg7keIuA4bW7nKgZhKZg9pFPuoYQSqoi4XN2aZMnlfrb9kS PU/YgsnUKt2rH8GDLhx6hAq3eIQbVARpIlEwXM8712MaYq5f+rah5w6zBf5+JhvgepnC Dihw== MIME-Version: 1.0 X-Received: by 10.50.45.97 with SMTP id l1mr6489850igm.5.1372339563228; Thu, 27 Jun 2013 06:26:03 -0700 (PDT) Received: by 10.64.128.234 with HTTP; Thu, 27 Jun 2013 06:26:03 -0700 (PDT) In-Reply-To: <0BB3B561D7068A4E89FD8E9ABFB538BEB3B2E44330@PG-ITMSG03.altera.priv.altera.com> References: <0BB3B561D7068A4E89FD8E9ABFB538BEB3B2E44330@PG-ITMSG03.altera.priv.altera.com> Date: Thu, 27 Jun 2013 08:26:03 -0500 Message-ID: From: Chin Liang See To: ZY - u-boot X-Mailman-Approved-At: Thu, 27 Jun 2013 15:42:58 +0200 Cc: ZY - pavel , clsee@altera.com, ZY - sr Subject: [U-Boot] [PATCH1/1] socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See Reviewed-by: Pavel Machek --- include/configs/socfpga_cyclone5.h | 28 +++++++++++++++++++++------- 1 files changed, 21 insertions(+), 7 deletions(-) -- 1.7.7.4 diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 5633d2a..86563b7 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -22,6 +22,8 @@ /* * High level configuration */ +/* Running on virtual target or real hardware */ #define +CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_ARMV7 #define CONFIG_L2_OFF @@ -32,11 +34,12 @@ #define CONFIG_SINGLE_BOOTLOADER #define CONFIG_SOCFPGA +/* base address for .text section */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TEXT_BASE 0x08000040 -#define V_NS16550_CLK 1000000 -#define CONFIG_BAUDRATE 57600 -#define CONFIG_SYS_HZ 1000 -#define CONFIG_TIMER_CLOCK_KHZ 2400 +#else +#define CONFIG_SYS_TEXT_BASE 0x01000040 +#endif #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* Console I/O Buffer Size */ @@ -165,7 +168,7 @@ /* SDRAM Bank #1 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* SDRAM memory size */ -#define PHYS_SDRAM_1_SIZE 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x40000000 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_START 0x00000000 @@ -181,8 +184,13 @@ #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 UART0_BASE - #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define V_NS16550_CLK 1000000 +#else +#define V_NS16550_CLK 100000000 +#endif +#define CONFIG_BAUDRATE 115200 /* * FLASH @@ -195,9 +203,15 @@ /* This timer use eosc1 where the clock frequency is fixed * throughout any condition */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS - /* reload value when timer count to zero */ #define TIMER_LOAD_VAL 0xFFFFFFFF +/* Timer info */ +#define CONFIG_SYS_HZ 1000 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_TIMER_CLOCK_KHZ 2400 +#else +#define CONFIG_TIMER_CLOCK_KHZ 25000 +#endif #define CONFIG_ENV_IS_NOWHERE