Patchwork [AArch64,ILP32] 4/5 Change tests to be ILP32-friendly

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Submitter Yufeng Zhang
Date June 26, 2013, 10:41 p.m.
Message ID <51CB6E02.9000505@arm.com>
Download mbox | patch
Permalink /patch/254909/
State New
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Comments

Yufeng Zhang - June 26, 2013, 10:41 p.m.
The attached patch fixes a few gcc test cases.


Thanks,
Yufeng


gcc/testsuite/

	* gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32.
	* gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field
	type from long to long long.
	* gcc.target/aarch64/atomic-op-long.c: Update dg-final directives
	to have effective-target keywords of lp64 and ilp32.
	* gcc.target/aarch64/fcvt_double_int.c: Likewise.
	* gcc.target/aarch64/fcvt_double_long.c: Likewise.
	* gcc.target/aarch64/fcvt_double_uint.c: Likewise.
	* gcc.target/aarch64/fcvt_double_ulong.c: Likewise.
	* gcc.target/aarch64/fcvt_float_int.c: Likewise.
	* gcc.target/aarch64/fcvt_float_long.c: Likewise.
	* gcc.target/aarch64/fcvt_float_uint.c: Likewise.
	* gcc.target/aarch64/fcvt_float_ulong.c: Likewise.
	* gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long long'.
Yufeng Zhang - July 18, 2013, 10:29 a.m.
Ping~

Thanks,
Yufeng

On 06/26/13 23:41, Yufeng Zhang wrote:
> The attached patch fixes a few gcc test cases.
>
>
> Thanks,
> Yufeng
>
>
> gcc/testsuite/
>
> 	* gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32.
> 	* gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field
> 	type from long to long long.
> 	* gcc.target/aarch64/atomic-op-long.c: Update dg-final directives
> 	to have effective-target keywords of lp64 and ilp32.
> 	* gcc.target/aarch64/fcvt_double_int.c: Likewise.
> 	* gcc.target/aarch64/fcvt_double_long.c: Likewise.
> 	* gcc.target/aarch64/fcvt_double_uint.c: Likewise.
> 	* gcc.target/aarch64/fcvt_double_ulong.c: Likewise.
> 	* gcc.target/aarch64/fcvt_float_int.c: Likewise.
> 	* gcc.target/aarch64/fcvt_float_long.c: Likewise.
> 	* gcc.target/aarch64/fcvt_float_uint.c: Likewise.
> 	* gcc.target/aarch64/fcvt_float_ulong.c: Likewise.
> 	* gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long long'.
Marcus Shawcroft - July 19, 2013, 9:17 a.m.
On 26 June 2013 23:41, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:

> gcc/testsuite/
>
>         * gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32.
>         * gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field
>         type from long to long long.
>         * gcc.target/aarch64/atomic-op-long.c: Update dg-final directives
>         to have effective-target keywords of lp64 and ilp32.
>         * gcc.target/aarch64/fcvt_double_int.c: Likewise.
>         * gcc.target/aarch64/fcvt_double_long.c: Likewise.
>         * gcc.target/aarch64/fcvt_double_uint.c: Likewise.
>         * gcc.target/aarch64/fcvt_double_ulong.c: Likewise.
>         * gcc.target/aarch64/fcvt_float_int.c: Likewise.
>         * gcc.target/aarch64/fcvt_float_long.c: Likewise.
>         * gcc.target/aarch64/fcvt_float_uint.c: Likewise.
>         * gcc.target/aarch64/fcvt_float_ulong.c: Likewise.
>         * gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long
> long'.
>

OK
/Marcus

Patch

diff --git a/gcc/testsuite/gcc.dg/20020219-1.c b/gcc/testsuite/gcc.dg/20020219-1.c
index ffdf19a..d2ba755 100644
--- a/gcc/testsuite/gcc.dg/20020219-1.c
+++ b/gcc/testsuite/gcc.dg/20020219-1.c
@@ -13,6 +13,7 @@ 
 /* { dg-do run } */
 /* { dg-options "-O2" } */
 /* { dg-options "-O2 -mdisable-indexing" { target hppa*-*-hpux* } } */
+/* { dg-skip-if "" { aarch64*-*-* && ilp32 } { "*" } { "" } } */
 /* { dg-skip-if "" { "ia64-*-hpux*" } "*" "-mlp64" } */
 /* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } { "*" } { "" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
index b611e9b..2ebecee 100644
--- a/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
+++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
@@ -9,10 +9,10 @@ 
 
 struct y
 {
-  long p;
-  long q;
-  long r;
-  long s;
+  long long p;
+  long long q;
+  long long r;
+  long long s;
 } v = { 1, 2, 3, 4 };
 
 struct z
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
index 9468ef4..0672d48 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
@@ -39,5 +39,7 @@  atomic_fetch_or_RELAXED (long a)
   return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
 }
 
-/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
-/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
index 697aab1..e539909 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
@@ -8,8 +8,10 @@ 
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
index edf640b..5eb36ff 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
@@ -7,7 +7,11 @@ 
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
index a1fae76..59be475 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
@@ -8,8 +8,10 @@ 
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
 /* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
index f95fe55..55723cf 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
@@ -7,9 +7,15 @@ 
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
index ac15098..2e10e2d 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
@@ -8,8 +8,10 @@ 
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
index 928ac52..1debf71 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
@@ -7,7 +7,11 @@ 
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
index a7d1868..c0b0c69 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
@@ -8,8 +8,10 @@ 
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
 /* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
index ab6f46e..07309e2 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
@@ -7,9 +7,15 @@ 
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c b/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
index 1f86eae..f8cfecc 100644
--- a/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
@@ -4,11 +4,11 @@ 
 typedef signed char S8_t;
 typedef signed short S16_t;
 typedef signed int S32_t;
-typedef signed long S64_t;
+typedef signed long long S64_t;
 typedef signed char *__restrict__ pS8_t;
 typedef signed short *__restrict__ pS16_t;
 typedef signed int *__restrict__ pS32_t;
-typedef signed long *__restrict__ pS64_t;
+typedef signed long long *__restrict__ pS64_t;
 typedef unsigned char U8_t;
 typedef unsigned short U16_t;
 typedef unsigned int U32_t;
@@ -16,7 +16,7 @@  typedef unsigned long U64_t;
 typedef unsigned char *__restrict__ pU8_t;
 typedef unsigned short *__restrict__ pU16_t;
 typedef unsigned int *__restrict__ pU32_t;
-typedef unsigned long *__restrict__ pU64_t;
+typedef unsigned long long *__restrict__ pU64_t;
 
 extern void abort ();