Patchwork [v2,4/9] tcg-ppc64: Don't implement rem

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Submitter Richard Henderson
Date June 26, 2013, 8:52 p.m.
Message ID <1372279929-28836-5-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/254864/
State New
Headers show

Comments

Richard Henderson - June 26, 2013, 8:52 p.m.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ppc64/tcg-target.c | 26 --------------------------
 tcg/ppc64/tcg-target.h |  4 ++--
 2 files changed, 2 insertions(+), 28 deletions(-)
Andreas Färber - July 2, 2013, 7:34 p.m.
Am 26.06.2013 22:52, schrieb Richard Henderson:
> Signed-off-by: Richard Henderson <rth@twiddle.net>

Reviewed-by: Andreas Färber <afaerber@suse.de>

Andreas

> ---
>  tcg/ppc64/tcg-target.c | 26 --------------------------
>  tcg/ppc64/tcg-target.h |  4 ++--
>  2 files changed, 2 insertions(+), 28 deletions(-)
> 
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index 606b73d..0678de2 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -1617,18 +1617,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
>          tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
>          break;
>  
> -    case INDEX_op_rem_i32:
> -        tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
> -        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
> -        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
> -        break;
> -
> -    case INDEX_op_remu_i32:
> -        tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
> -        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
> -        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
> -        break;
> -
>      case INDEX_op_shl_i32:
>          if (const_args[2]) {
>              tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
> @@ -1786,16 +1774,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
>      case INDEX_op_divu_i64:
>          tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
>          break;
> -    case INDEX_op_rem_i64:
> -        tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
> -        tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
> -        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
> -        break;
> -    case INDEX_op_remu_i64:
> -        tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
> -        tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
> -        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
> -        break;
>  
>      case INDEX_op_qemu_ld8u:
>          tcg_out_qemu_ld (s, args, 0);
> @@ -2064,8 +2042,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>      { INDEX_op_mul_i32, { "r", "r", "rI" } },
>      { INDEX_op_div_i32, { "r", "r", "r" } },
>      { INDEX_op_divu_i32, { "r", "r", "r" } },
> -    { INDEX_op_rem_i32, { "r", "r", "r" } },
> -    { INDEX_op_remu_i32, { "r", "r", "r" } },
>      { INDEX_op_sub_i32, { "r", "rI", "ri" } },
>      { INDEX_op_and_i32, { "r", "r", "ri" } },
>      { INDEX_op_or_i32, { "r", "r", "ri" } },
> @@ -2108,8 +2084,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>      { INDEX_op_mul_i64, { "r", "r", "rI" } },
>      { INDEX_op_div_i64, { "r", "r", "r" } },
>      { INDEX_op_divu_i64, { "r", "r", "r" } },
> -    { INDEX_op_rem_i64, { "r", "r", "r" } },
> -    { INDEX_op_remu_i64, { "r", "r", "r" } },
>  
>      { INDEX_op_neg_i64, { "r", "r" } },
>      { INDEX_op_not_i64, { "r", "r" } },
> diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
> index 7c600f1..48fc6e2 100644
> --- a/tcg/ppc64/tcg-target.h
> +++ b/tcg/ppc64/tcg-target.h
> @@ -76,7 +76,7 @@ typedef enum {
>  
>  /* optional instructions */
>  #define TCG_TARGET_HAS_div_i32          1
> -#define TCG_TARGET_HAS_rem_i32          1
> +#define TCG_TARGET_HAS_rem_i32          0
>  #define TCG_TARGET_HAS_rot_i32          1
>  #define TCG_TARGET_HAS_ext8s_i32        1
>  #define TCG_TARGET_HAS_ext16s_i32       1
> @@ -97,7 +97,7 @@ typedef enum {
>  #define TCG_TARGET_HAS_muls2_i32        0
>  
>  #define TCG_TARGET_HAS_div_i64          1
> -#define TCG_TARGET_HAS_rem_i64          1
> +#define TCG_TARGET_HAS_rem_i64          0
>  #define TCG_TARGET_HAS_rot_i64          1
>  #define TCG_TARGET_HAS_ext8s_i64        1
>  #define TCG_TARGET_HAS_ext16s_i64       1
>

Patch

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 606b73d..0678de2 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1617,18 +1617,6 @@  static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
         tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
         break;
 
-    case INDEX_op_rem_i32:
-        tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-
-    case INDEX_op_remu_i32:
-        tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-
     case INDEX_op_shl_i32:
         if (const_args[2]) {
             tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
@@ -1786,16 +1774,6 @@  static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
     case INDEX_op_divu_i64:
         tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
         break;
-    case INDEX_op_rem_i64:
-        tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-    case INDEX_op_remu_i64:
-        tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
 
     case INDEX_op_qemu_ld8u:
         tcg_out_qemu_ld (s, args, 0);
@@ -2064,8 +2042,6 @@  static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_mul_i32, { "r", "r", "rI" } },
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
-    { INDEX_op_rem_i32, { "r", "r", "r" } },
-    { INDEX_op_remu_i32, { "r", "r", "r" } },
     { INDEX_op_sub_i32, { "r", "rI", "ri" } },
     { INDEX_op_and_i32, { "r", "r", "ri" } },
     { INDEX_op_or_i32, { "r", "r", "ri" } },
@@ -2108,8 +2084,6 @@  static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_mul_i64, { "r", "r", "rI" } },
     { INDEX_op_div_i64, { "r", "r", "r" } },
     { INDEX_op_divu_i64, { "r", "r", "r" } },
-    { INDEX_op_rem_i64, { "r", "r", "r" } },
-    { INDEX_op_remu_i64, { "r", "r", "r" } },
 
     { INDEX_op_neg_i64, { "r", "r" } },
     { INDEX_op_not_i64, { "r", "r" } },
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 7c600f1..48fc6e2 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -76,7 +76,7 @@  typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          1
-#define TCG_TARGET_HAS_rem_i32          1
+#define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
@@ -97,7 +97,7 @@  typedef enum {
 #define TCG_TARGET_HAS_muls2_i32        0
 
 #define TCG_TARGET_HAS_div_i64          1
-#define TCG_TARGET_HAS_rem_i64          1
+#define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_rot_i64          1
 #define TCG_TARGET_HAS_ext8s_i64        1
 #define TCG_TARGET_HAS_ext16s_i64       1