From patchwork Wed Jun 26 09:28:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 254671 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 614192C008E for ; Wed, 26 Jun 2013 19:29:39 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751786Ab3FZJ3c (ORCPT ); Wed, 26 Jun 2013 05:29:32 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8599 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751785Ab3FZJ3b (ORCPT ); Wed, 26 Jun 2013 05:29:31 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 26 Jun 2013 02:29:06 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 26 Jun 2013 02:29:29 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 26 Jun 2013 02:29:29 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.298.1; Wed, 26 Jun 2013 02:29:30 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Wed, 26 Jun 2013 02:29:30 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r5Q9SmR6017123; Wed, 26 Jun 2013 02:29:29 -0700 (PDT) From: Hiroshi Doyu To: CC: , , Hiroshi Doyu Subject: [PATCH 21/23] iommu/tegra: smmu: Get swgroup ID from DT Date: Wed, 26 Jun 2013 12:28:24 +0300 Message-ID: <1372238906-9346-22-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.8.1.5 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Get swgroup ID from DT. "nvidia,swgroups" indicates which swgroup IDs a device belongs to. Signed-off-by: Hiroshi Doyu --- arch/arm/boot/dts/tegra30.dtsi | 1 - drivers/iommu/tegra-smmu.c | 20 +++++++++++++++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 7c480f2..a116737 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -1,6 +1,5 @@ #include #include -#include #include #include "skeleton.dtsi" diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 50eb843..96dbef3 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -314,6 +314,24 @@ static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs) #define smmu_client_hwgrp(c) (c->as->smmu->swgroups) +static u64 tegra_smmu_of_get_swgids(struct device *dev) +{ + size_t bytes; + const char *propname = "nvidia,memory-clients"; + const __be32 *prop; + int i; + u64 swgids = 0; + + prop = of_get_property(dev->of_node, propname, &bytes); + if (!prop || !bytes) + return 0; + + for (i = 0; i < bytes / sizeof(u32); i++, prop++) + swgids |= 1ULL << be32_to_cpup(prop); + + return swgids; +} + static int __smmu_client_set_hwgrp(struct smmu_client *c, u64 map, int on) { @@ -725,7 +743,7 @@ static int smmu_iommu_attach_dev(struct iommu_domain *domain, return -ENOMEM; client->dev = dev; client->as = as; - map = smmu->swgroups; + map = tegra_smmu_of_get_swgids(dev); if (!map) return -EINVAL;