From patchwork Wed Jun 26 09:28:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 254668 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B480E2C0095 for ; Wed, 26 Jun 2013 19:29:37 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751784Ab3FZJ32 (ORCPT ); Wed, 26 Jun 2013 05:29:28 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:10213 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751785Ab3FZJ30 (ORCPT ); Wed, 26 Jun 2013 05:29:26 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 26 Jun 2013 02:28:53 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 26 Jun 2013 02:27:23 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 26 Jun 2013 02:27:23 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.298.1; Wed, 26 Jun 2013 02:29:26 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Wed, 26 Jun 2013 02:29:25 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r5Q9SmR3017123; Wed, 26 Jun 2013 02:29:24 -0700 (PDT) From: Hiroshi Doyu To: CC: , , Hiroshi Doyu Subject: [PATCH 18/23] iommu/tegra: smmu: Workaround PCIe IOMMU'able Date: Wed, 26 Jun 2013 12:28:21 +0300 Message-ID: <1372238906-9346-19-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.8.1.5 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Make PCIe work as it is. IOMMU support can be implemented later. Signed-off-by: Hiroshi Doyu --- drivers/iommu/tegra-smmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 64da08a..6e82df3 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -402,6 +402,9 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, for_each_set_bit(i, (unsigned long *)&map, sizeof(map) * BITS_PER_BYTE) { + if (i == SWGID_AFI) /* FIXME: IOMMU'able PCIe */ + continue; + offs = HWGRP_ASID_REG(i); val = smmu_read(smmu, offs); if (on) {