From patchwork Wed Jun 26 09:28:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 254660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C5B402C0095 for ; Wed, 26 Jun 2013 19:29:11 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751445Ab3FZJ3L (ORCPT ); Wed, 26 Jun 2013 05:29:11 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8561 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751447Ab3FZJ3K (ORCPT ); Wed, 26 Jun 2013 05:29:10 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 26 Jun 2013 02:28:45 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 26 Jun 2013 02:29:08 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 26 Jun 2013 02:29:08 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.298.1; Wed, 26 Jun 2013 02:29:09 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Wed, 26 Jun 2013 02:29:08 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r5Q9SmQr017123; Wed, 26 Jun 2013 02:29:07 -0700 (PDT) From: Hiroshi Doyu To: CC: , , Hiroshi Doyu Subject: [PATCH 08/23] ARM: dt: tegra114: Register AHB/IOMMU device first Date: Wed, 26 Jun 2013 12:28:11 +0300 Message-ID: <1372238906-9346-9-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.8.1.5 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Move up AHB/IOMMU to register them earlier than others. IOMMU needs AHB, and IOMMU needs to register all platform devices as IOMMU'able. So AHB/IOMMU needs to be instanciated at very beginning. Signed-off-by: Hiroshi Doyu --- arch/arm/boot/dts/tegra114.dtsi | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 980a3b1..180186f 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -16,6 +16,23 @@ serial3 = &uartd; }; + /* FIXME: ahb/iommu needs to be populated first. */ + ahb: ahb { + compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; + reg = <0x6000c004 0x14c>; + }; + + iommu { + compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; + reg = <0x70019010 0x02c + 0x700191f0 0x010 + 0x70019228 0x074>; + nvidia,#asids = <4>; + dma-window = <0 0x40000000>; + nvidia,swgroups = <0x00000000 0x01b659fe>; + nvidia,ahb = <&ahb>; + }; + gic: interrupt-controller { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; @@ -84,11 +101,6 @@ clocks = <&tegra_car TEGRA114_CLK_APBDMA>; }; - ahb: ahb { - compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; - reg = <0x6000c004 0x14c>; - }; - gpio: gpio { compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; @@ -317,17 +329,6 @@ clock-names = "pclk", "clk32k_in"; }; - iommu { - compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; - reg = <0x70019010 0x02c - 0x700191f0 0x010 - 0x70019228 0x074>; - nvidia,#asids = <4>; - dma-window = <0 0x40000000>; - nvidia,swgroups = <0x00000000 0x01b659fe>; - nvidia,ahb = <&ahb>; - }; - ahub { compatible = "nvidia,tegra114-ahub"; reg = <0x70080000 0x200>,