Patchwork [04/23] ARM: dt: tegra30: Register AHB/IOMMU device first

login
register
mail settings
Submitter Hiroshi Doyu
Date June 26, 2013, 9:28 a.m.
Message ID <1372238906-9346-5-git-send-email-hdoyu@nvidia.com>
Download mbox | patch
Permalink /patch/254656/
State Superseded, archived
Headers show

Comments

Hiroshi Doyu - June 26, 2013, 9:28 a.m.
Move up AHB/IOMMU to register them earlier than others. IOMMU needs
AHB, and IOMMU needs to register all platform devices as
IOMMU'able. So AHB/IOMMU needs to be instanciated at very beginning.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 arch/arm/boot/dts/tegra30.dtsi | 33 +++++++++++++++++----------------
 1 file changed, 17 insertions(+), 16 deletions(-)
Thierry Reding - June 26, 2013, 10:45 a.m.
On Wed, Jun 26, 2013 at 12:28:07PM +0300, Hiroshi Doyu wrote:
> Move up AHB/IOMMU to register them earlier than others. IOMMU needs
> AHB, and IOMMU needs to register all platform devices as
> IOMMU'able. So AHB/IOMMU needs to be instanciated at very beginning.
> 
> Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
> ---
>  arch/arm/boot/dts/tegra30.dtsi | 33 +++++++++++++++++----------------
>  1 file changed, 17 insertions(+), 16 deletions(-)

This just happens to work because DTC keeps the order from the DTS in
the DTB and the Linux implementation sequentially instantiates devices
from DT nodes. Neither should be assumed though when writing DTS files.
Other implementations (DTC or OS) could do things differently.

But if I understand correctly there is another solution which should
solve this issue properly.

Thierry
Hiroshi Doyu - June 26, 2013, 11:06 a.m.
Thierry Reding <thierry.reding@gmail.com> wrote @ Wed, 26 Jun 2013 12:45:14 +0200:

> * PGP Signed by an unknown key
> 
> On Wed, Jun 26, 2013 at 12:28:07PM +0300, Hiroshi Doyu wrote:
> > Move up AHB/IOMMU to register them earlier than others. IOMMU needs
> > AHB, and IOMMU needs to register all platform devices as
> > IOMMU'able. So AHB/IOMMU needs to be instanciated at very beginning.
> > 
> > Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
> > ---
> >  arch/arm/boot/dts/tegra30.dtsi | 33 +++++++++++++++++----------------
> >  1 file changed, 17 insertions(+), 16 deletions(-)
> 
> This just happens to work because DTC keeps the order from the DTS in
> the DTB and the Linux implementation sequentially instantiates devices
> from DT nodes. Neither should be assumed though when writing DTS files.
> Other implementations (DTC or OS) could do things differently.
> 
> But if I understand correctly there is another solution which should
> solve this issue properly.

As you've noticed:

https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-June/036746.html
--
To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Patch

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 3fcee3f..7c480f2 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -17,6 +17,23 @@ 
 		serial4 = &uarte;
 	};
 
+	/* FIXME: ahb/iommu needs to be populated first. */
+	ahb: ahb {
+		compatible = "nvidia,tegra30-ahb";
+		reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
+	};
+
+	iommu {
+		compatible = "nvidia,tegra30-smmu";
+		reg = <0x7000f010 0x02c
+		       0x7000f1f0 0x010
+		       0x7000f228 0x05c>;
+		nvidia,#asids = <4>;		/* # of ASIDs */
+		dma-window = <0 0x40000000>;	/* IOVA start & length */
+		nvidia,swgroups = <0x00000000 0x000779ff>;
+		nvidia,ahb = <&ahb>;
+	};
+
 	host1x {
 		compatible = "nvidia,tegra30-host1x", "simple-bus";
 		reg = <0x50000000 0x00024000>;
@@ -213,11 +230,6 @@ 
 		clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 	};
 
-	ahb: ahb {
-		compatible = "nvidia,tegra30-ahb";
-		reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
-	};
-
 	gpio: gpio {
 		compatible = "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;
@@ -469,17 +481,6 @@ 
 		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
-	iommu {
-		compatible = "nvidia,tegra30-smmu";
-		reg = <0x7000f010 0x02c
-		       0x7000f1f0 0x010
-		       0x7000f228 0x05c>;
-		nvidia,#asids = <4>;		/* # of ASIDs */
-		dma-window = <0 0x40000000>;	/* IOVA start & length */
-		nvidia,swgroups = <0x00000000 0x000779ff>;
-		nvidia,ahb = <&ahb>;
-	};
-
 	ahub {
 		compatible = "nvidia,tegra30-ahub";
 		reg = <0x70080000 0x200