From patchwork Tue Jun 25 17:04:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Bolton X-Patchwork-Id: 254250 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 94BDA2C007A for ; Wed, 26 Jun 2013 03:05:20 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=OGyrYbTEDLkCLajI8Huge/fCuf+gx5pBbUPmFOe1dWO9YGvYLAKwb ++sgMSwmq9ZhdChvecfmdWzd1dM0nIK0LMJ4LwWRr3+/G4nr/qnNhw/OCZEiTVPm 6YIPI+0gRUn0DrogEUJ3q2e4rQ/+nNuOFOqpfL2bKOEtMs28GyMOes= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=H7sNfNS+YAHipdidxhcFyvZBxQo=; b=Po2RezHtWzD7/X9euuKd GY4MUcEhIW8thbjpU+wmFnKJlz1MPHWMjCHeo4iSKo+XJotpUJGYw727n987paoS PyGo8kd6aZUdqGoQkeITdMWvFk1/Jc4hvYeXRyyXGkAwxI0rC6sSd45q8OGgxjYq M57kUKanx7qfqcSpVcCO1QM= Received: (qmail 17933 invoked by alias); 25 Jun 2013 17:05:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17922 invoked by uid 89); 25 Jun 2013 17:05:13 -0000 X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL, BAYES_00, MSGID_MULTIPLE_AT, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=no version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 25 Jun 2013 17:05:12 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 25 Jun 2013 18:05:09 +0100 Received: from E102352xp ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 25 Jun 2013 18:05:07 +0100 From: "Ian Bolton" To: Subject: [PATCH, AArch64] Support abs standard pattern for DI mode Date: Tue, 25 Jun 2013 18:04:41 +0100 Message-ID: <000401ce71c6$15630fc0$40292f40$@bolton@arm.com> MIME-Version: 1.0 X-MC-Unique: 113062518050905901 X-Virus-Found: No Hi, I'm adding support for abs standard pattern name for DI mode, via the ABS instruction in FP registers and the EOR/SUB combo in GP registers. Regression tests for Linux and bare-metal all passed. OK for trunk? Cheers, Ian 2013-06-25 Ian Bolton gcc/ * config/aarch64/aarch64-simd.md (absdi2): Support abs for DI mode. testsuite/ * gcc.target/aarch64/abs_1.c: New test. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index e88e5be..3700977 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2003,6 +2003,38 @@ (set_attr "mode" "SI")] ) +(define_insn_and_split "absdi2" + [(set (match_operand:DI 0 "register_operand" "=r,w") + (abs:DI (match_operand:DI 1 "register_operand" "r,w"))) + (clobber (match_scratch:DI 2 "=&r,X"))] + "" + "@ + # + abs\\t%d0, %d1" + "reload_completed + && GP_REGNUM_P (REGNO (operands[0])) + && GP_REGNUM_P (REGNO (operands[1]))" + [(const_int 0)] + { + emit_insn (gen_rtx_SET (VOIDmode, operands[2], + gen_rtx_XOR (DImode, + gen_rtx_ASHIFTRT (DImode, + operands[1], + GEN_INT (63)), + operands[1]))); + emit_insn (gen_rtx_SET (VOIDmode, + operands[0], + gen_rtx_MINUS (DImode, + operands[2], + gen_rtx_ASHIFTRT (DImode, + operands[1], + GEN_INT (63))))); + DONE; + } + [(set_attr "v8type" "alu") + (set_attr "mode" "DI")] +) + (define_insn "neg2" [(set (match_operand:GPI 0 "register_operand" "=r") (neg:GPI (match_operand:GPI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/aarch64/abs_1.c b/gcc/testsuite/gcc.target/aarch64/abs_1.c new file mode 100644 index 0000000..938bc84 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/abs_1.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-inline --save-temps" } */ + +extern long long llabs (long long); +extern void abort (void); + +long long +abs64 (long long a) +{ + /* { dg-final { scan-assembler "eor\t" } } */ + /* { dg-final { scan-assembler "sub\t" } } */ + return llabs (a); +} + +long long +abs64_in_dreg (long long a) +{ + /* { dg-final { scan-assembler "abs\td\[0-9\]+, d\[0-9\]+" } } */ + register long long x asm ("d8") = a; + register long long y asm ("d9"); + asm volatile ("" : : "w" (x)); + y = llabs (x); + asm volatile ("" : : "w" (y)); + return y; +} + +int +main (void) +{ + volatile long long ll0 = 0LL, ll1 = 1LL, llm1 = -1LL; + + if (abs64 (ll0) != 0LL) + abort (); + + if (abs64 (ll1) != 1LL) + abort (); + + if (abs64 (llm1) != 1LL) + abort (); + + if (abs64_in_dreg (ll0) != 0LL) + abort (); + + if (abs64_in_dreg (ll1) != 1LL) + abort (); + + if (abs64_in_dreg (llm1) != 1LL) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */