From patchwork Fri Jun 21 20:23:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 253312 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 11CF92C03EB for ; Sat, 22 Jun 2013 06:24:01 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1945999Ab3FUUYA (ORCPT ); Fri, 21 Jun 2013 16:24:00 -0400 Received: from avon.wwwdotorg.org ([70.85.31.133]:41986 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1945961Ab3FUUX7 (ORCPT ); Fri, 21 Jun 2013 16:23:59 -0400 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id AA22362F2; Fri, 21 Jun 2013 14:33:28 -0600 (MDT) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 22BBBE40EB; Fri, 21 Jun 2013 14:23:58 -0600 (MDT) From: Stephen Warren To: Thierry Reding Cc: linux-tegra@vger.kernel.org, Stephen Warren Subject: [PATCH] ARM: tegra: Fix Beaver's PCIe lane configuration Date: Fri, 21 Jun 2013 14:23:52 -0600 Message-Id: <1371846232-31163-1-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.8.1.5 X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.97.7 at avon.wwwdotorg.org X-Virus-Status: Clean Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Stephen Warren Beaver's PCIe lane configuration most closely matches x2 x2 x2 rather than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 and 5 are used, and the only way those align is with a x2 x2 x2 configuration. Also, disable root port 1; there's nothing connected to it. Root port 0 is the on-board PCIe Ethernet, and port 2 is the mini-PCIe slot. Signed-off-by: Stephen Warren --- This is to be applied to Thierry's WIP PCIe driver branch. arch/arm/boot/dts/tegra30-beaver.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index c42dd9b..e0b8e9c 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -18,16 +18,16 @@ pci@1,0 { status = "okay"; - nvidia,num-lanes = <4>; + nvidia,num-lanes = <2>; }; pci@2,0 { - status = "okay"; - nvidia,num-lanes = <1>; + nvidia,num-lanes = <2>; }; pci@3,0 { - nvidia,num-lanes = <1>; + status = "okay"; + nvidia,num-lanes = <2>; }; };