From patchwork Thu Jun 20 08:04:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ying.zhang@freescale.com X-Patchwork-Id: 252808 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id F2F8D2C007B for ; Thu, 20 Jun 2013 18:55:48 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BE13D4A151; Thu, 20 Jun 2013 10:55:34 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3nzYRJ+sFTdZ; Thu, 20 Jun 2013 10:55:34 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3ED7E4A163; Thu, 20 Jun 2013 10:54:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AFF614A131 for ; Thu, 20 Jun 2013 10:54:44 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0C2FMy6IV0cF for ; Thu, 20 Jun 2013 10:54:39 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from co9outboundpool.messaging.microsoft.com (co9ehsobe005.messaging.microsoft.com [207.46.163.28]) by theia.denx.de (Postfix) with ESMTPS id 3669D4A143 for ; Thu, 20 Jun 2013 10:54:04 +0200 (CEST) Received: from mail80-co9-R.bigfish.com (10.236.132.252) by CO9EHSOBE040.bigfish.com (10.236.130.103) with Microsoft SMTP Server id 14.1.225.23; Thu, 20 Jun 2013 08:54:00 +0000 Received: from mail80-co9 (localhost [127.0.0.1]) by mail80-co9-R.bigfish.com (Postfix) with ESMTP id DC834120136; Thu, 20 Jun 2013 08:54:00 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1f42h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ah1fc6hzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h1354h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e23h1155h) Received: from mail80-co9 (localhost.localdomain [127.0.0.1]) by mail80-co9 (MessageSwitch) id 1371718438132718_11093; Thu, 20 Jun 2013 08:53:58 +0000 (UTC) Received: from CO9EHSMHS002.bigfish.com (unknown [10.236.132.240]) by mail80-co9.bigfish.com (Postfix) with ESMTP id 1E2B1E091E; Thu, 20 Jun 2013 08:53:58 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS002.bigfish.com (10.236.130.12) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 20 Jun 2013 08:53:53 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.2.328.11; Thu, 20 Jun 2013 08:53:53 +0000 Received: from localhost.localdomain (tank.ap.freescale.net [10.193.20.104]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r5K8rOuE003327; Thu, 20 Jun 2013 01:53:51 -0700 From: To: Date: Thu, 20 Jun 2013 16:04:26 +0800 Message-ID: <1371715468-21120-8-git-send-email-ying.zhang@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1371715468-21120-1-git-send-email-ying.zhang@freescale.com> References: <1371715468-21120-1-git-send-email-ying.zhang@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: scottwood@freescale.com, afleming@gmail.com, X.Xie@freescale.com, Ying Zhang Subject: [U-Boot] [PATCH 08/10 v5] powerpc/p1022ds: boot from spi flash with SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Ying Zhang Support to boot from spi flash. This patch is on top of the patch: powerpc/p1022ds: boot from SD Card with SPL Signed-off-by: Ying Zhang --- Compared with the original version, Changed as below: 1. Split from "boot from SD card/SPI flash with SPL". 2. No change. 3. No change. 4. No change. board/freescale/p1022ds/spl.c | 12 +++++- drivers/mtd/spi/Makefile | 1 + drivers/mtd/spi/fsl_espi_spl.c | 78 ++++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi_flash.c | 2 + include/configs/P1022DS.h | 36 +++++++++++++++---- 5 files changed, 120 insertions(+), 9 deletions(-) create mode 100644 drivers/mtd/spi/fsl_espi_spl.c diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index 40f000f..1dd9050 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -21,13 +21,12 @@ #include #include -#include -#include #include #include #include #include "../common/ngpixis.h" #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -54,6 +53,11 @@ void board_init_f(ulong bootflag) setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); +#ifdef CONFIG_SPL_SPI_BOOT + /* Enable the SPI */ + clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); +#endif + /* Read back the register to synchronize the write. */ in_be32(&gur->pmuxcr); @@ -67,6 +71,8 @@ void board_init_f(ulong bootflag) bus_clk / 16 / CONFIG_BAUDRATE); #ifdef CONFIG_SPL_MMC_BOOT puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); #endif /* copy code to RAM and jump to it - this should not return */ @@ -108,5 +114,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); #endif } diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 90f8392..5f130d5 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libspi_flash.o ifdef CONFIG_SPL_BUILD COBJS-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o +COBJS-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o endif COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c new file mode 100644 index 0000000..8375a75 --- /dev/null +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -0,0 +1,78 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +#define ESPI_BOOT_IMAGE_SIZE 0x48 +#define ESPI_BOOT_IMAGE_ADDR 0x50 +#define CONFIG_CFG_DATA_SECTOR 0 + +/* + * The main entry for SPI booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from SPI into SDRAM and starts it from there. + */ +void spi_boot(void) +{ + void (*uboot)(void) __noreturn; + u32 offset, code_len, i; + unsigned char *buf = NULL; + struct spi_flash *flash; + + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (flash == NULL) { + puts("\nspi_flash_probe failed"); + hang(); + } + + /* + * Load U-Boot image from SPI flash into RAM + */ + buf = malloc(flash->page_size); + if (buf == NULL) { + puts("\nmalloc failed"); + hang(); + } + memset(buf, 0, flash->page_size); + + spi_flash_read(flash, CONFIG_CFG_DATA_SECTOR, \ + flash->page_size, (void *)buf); + offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR); + /* Skip spl code */ + offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; + /* Get the code size from offset 0x48 */ + code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE); + /* Skip spl code */ + code_len = code_len - CONFIG_SPL_MAX_SIZE; + /* copy code to DDR */ + spi_flash_read(flash, offset, code_len, \ + (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST); + /* + * Jump to U-Boot image + */ + flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, \ + code_len); + uboot = (void *) CONFIG_SYS_SPI_FLASH_U_BOOT_START; + (*uboot)(); +} diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 0e38f59..3ffe89f 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -428,12 +428,14 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, goto err_manufacturer_probe; } #endif +#ifndef CONFIG_SPL_BUILD printf("SF: Detected %s with page size ", flash->name); print_size(flash->sector_size, ", total "); print_size(flash->size, ""); if (flash->memory_map) printf(", mapped at %p", flash->memory_map); puts("\n"); +#endif spi_release_bus(spi); diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index bfeaf6a..467c838 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -48,11 +48,33 @@ #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_SPI_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif #define CONFIG_NAND_FSL_ELBC @@ -318,7 +340,7 @@ * Config the L2 Cache as L2 SRAM */ #if defined(CONFIG_SPL_BUILD) -#if defined(CONFIG_SDCARD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_L2_SIZE (256 << 10) @@ -563,7 +585,7 @@ /* * Environment */ -#ifdef CONFIG_RAMBOOT_SPIFLASH +#ifdef CONFIG_SPIFLASH #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0