From patchwork Tue Jun 18 11:10:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 252232 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 23AF92C029B for ; Tue, 18 Jun 2013 21:17:46 +1000 (EST) Received: from localhost ([::1]:40440 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uotux-0003xM-U0 for incoming@patchwork.ozlabs.org; Tue, 18 Jun 2013 07:17:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47352) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UotuZ-0003rG-An for qemu-devel@nongnu.org; Tue, 18 Jun 2013 07:17:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UotuY-0001mw-2y for qemu-devel@nongnu.org; Tue, 18 Jun 2013 07:17:19 -0400 Received: from mail-pb0-x230.google.com ([2607:f8b0:400e:c01::230]:39827) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UotuX-0001mn-T5 for qemu-devel@nongnu.org; Tue, 18 Jun 2013 07:17:18 -0400 Received: by mail-pb0-f48.google.com with SMTP id ma3so3776508pbc.7 for ; Tue, 18 Jun 2013 04:17:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=UOFJTWXonbA2XaOyWKdc0vA1mkyJz1dcfnS5L0qNcO4=; b=NLOWFECt0EshqD0Fwq+7fJ1oyfcDTQjPAry7bmv2SFjVu94aGPHfyeZ43kBKttF8rL gr481bNbigpuqhaKZZ2hI2on1bcDogW8brJnVFlMo0QsAv19jP7gA6EN6FcLwcZl7CW5 WjJSnFyqi0I37luH28syYerqp82QOUusYuwIiIi//P58qUmZBiFPhzE/O+ZEp2Slebmx 4sq4RtBUtmfdKG5bu+0ET/KXa5BzK8myUZ8LtAQ9UXQ3+DIfeUT6XzJEZ8n/rXr2ys34 4KGOxPoX8k4MTYyYUwgLHiTrJgyghZHTmAld5ngKjFPUqCkoMjByj0jKr3AomRjTyXuD XMQw== X-Received: by 10.66.145.229 with SMTP id sx5mr1774418pab.11.1371554237189; Tue, 18 Jun 2013 04:17:17 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id e2sm17850660pbc.23.2013.06.18.04.17.10 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Tue, 18 Jun 2013 04:17:16 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: qemu-devel@nongnu.org Date: Tue, 18 Jun 2013 21:10:44 +1000 Message-Id: <267c3875ca8d6b674f8343de3d22caad8f551fe6.1371553360.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.8.3.rc1.44.gb387c77.dirty In-Reply-To: References: X-Gm-Message-State: ALoCoQkJUrKW923DDfdou13PQcXOsX2/np/r6pNK1QzzK6ccZnkGy5GGmnLlM7NLI2ZMrAxElnKp X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::230 Cc: peter.maydell@linaro.org, Peter Crosthwaite , afaerber@suse.de, edgar.iglesias@gmail.com Subject: [Qemu-devel] [PATCH v1 3/5] block/nand: QOM casting sweep X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite Define and use standard QOM cast macro. Remove usages of DO_UPCAST and direct -> style casting. Cc: afaerber@suse.de Signed-off-by: Peter Crosthwaite Reviewed-by: Andreas Färber --- hw/block/nand.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/hw/block/nand.c b/hw/block/nand.c index de0a022..d2469f5 100644 --- a/hw/block/nand.c +++ b/hw/block/nand.c @@ -82,6 +82,11 @@ struct NANDFlashState { uint32_t ioaddr_vmstate; }; +#define TYPE_NAND "nand" + +#define NAND(obj) \ + OBJECT_CHECK(NANDFlashState, (obj), TYPE_NAND) + static void mem_and(uint8_t *dest, const uint8_t *src, size_t n) { /* Like memcpy() but we logical-AND the data into the destination */ @@ -224,7 +229,7 @@ static const struct { static void nand_reset(DeviceState *dev) { - NANDFlashState *s = FROM_SYSBUS(NANDFlashState, SYS_BUS_DEVICE(dev)); + NANDFlashState *s = NAND(dev); s->cmd = NAND_CMD_READ0; s->addr = 0; s->addrlen = 0; @@ -279,7 +284,7 @@ static void nand_command(NANDFlashState *s) break; case NAND_CMD_RESET: - nand_reset(&s->busdev.qdev); + nand_reset(DEVICE(s)); break; case NAND_CMD_PAGEPROGRAM1: @@ -319,14 +324,14 @@ static void nand_command(NANDFlashState *s) static void nand_pre_save(void *opaque) { - NANDFlashState *s = opaque; + NANDFlashState *s = NAND(opaque); s->ioaddr_vmstate = s->ioaddr - s->io; } static int nand_post_load(void *opaque, int version_id) { - NANDFlashState *s = opaque; + NANDFlashState *s = NAND(opaque); if (s->ioaddr_vmstate > sizeof(s->io)) { return -EINVAL; @@ -365,7 +370,7 @@ static const VMStateDescription vmstate_nand = { static int nand_device_init(SysBusDevice *dev) { int pagesize; - NANDFlashState *s = FROM_SYSBUS(NANDFlashState, dev); + NANDFlashState *s = NAND(dev); s->buswidth = nand_flash_ids[s->chip_id].width >> 3; s->size = nand_flash_ids[s->chip_id].size << 20; @@ -436,7 +441,7 @@ static void nand_class_init(ObjectClass *klass, void *data) } static const TypeInfo nand_info = { - .name = "nand", + .name = TYPE_NAND, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(NANDFlashState), .class_init = nand_class_init, @@ -456,7 +461,8 @@ static void nand_register_types(void) void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale, uint8_t ce, uint8_t wp, uint8_t gnd) { - NANDFlashState *s = (NANDFlashState *) dev; + NANDFlashState *s = NAND(dev); + s->cle = cle; s->ale = ale; s->ce = ce; @@ -477,7 +483,8 @@ void nand_getpins(DeviceState *dev, int *rb) void nand_setio(DeviceState *dev, uint32_t value) { int i; - NANDFlashState *s = (NANDFlashState *) dev; + NANDFlashState *s = NAND(dev); + if (!s->ce && s->cle) { if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) { if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2) @@ -581,7 +588,7 @@ uint32_t nand_getio(DeviceState *dev) { int offset; uint32_t x = 0; - NANDFlashState *s = (NANDFlashState *) dev; + NANDFlashState *s = NAND(dev); /* Allow sequential reading */ if (!s->iolen && s->cmd == NAND_CMD_READ0) {