From patchwork Tue Jun 18 09:47:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 252208 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6AF732C0096 for ; Tue, 18 Jun 2013 19:53:46 +1000 (EST) Received: from localhost ([::1]:59070 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uosbg-0001gs-Ce for incoming@patchwork.ozlabs.org; Tue, 18 Jun 2013 05:53:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56712) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UosbJ-0001dL-PZ for qemu-devel@nongnu.org; Tue, 18 Jun 2013 05:53:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UosbH-0000KR-Vo for qemu-devel@nongnu.org; Tue, 18 Jun 2013 05:53:21 -0400 Received: from mail-pa0-x22d.google.com ([2607:f8b0:400e:c03::22d]:52841) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UosbH-0000K8-Pz for qemu-devel@nongnu.org; Tue, 18 Jun 2013 05:53:19 -0400 Received: by mail-pa0-f45.google.com with SMTP id bi5so3824513pad.18 for ; Tue, 18 Jun 2013 02:53:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=FVBOO23fvGmY5twO8xZGCBZgWV7Lo9t2sYSjNxHYtBI=; b=Rv16JIzMO5ED3GRboRCq3QbT8tBhaTi+h9bgfjenhpNPc4OSWM47u6ePxpb4IL+pqg OhVOIR7AzhC6Cz36r6hmUWRL3nw2TJ2LPVM/M56e6iCrCTFHRTgQU1sPwWIrwRRe+zhw 1fF8XAK/SUL+LynEWR0zfeO4wIm3AKwgv2vSkjmV+ThA5UqMcVIgd16JrRArBTjnvKdW fUTI7X3PyOdBQmXJQvqDVK4vlzmU2rEfYLCMpxBMabOyFOo/4rPTsyGvWU29/Dq2UBRX p+2r6L/SzRDbBUJNErZ5iAKHOE1rfsrUTAf9GWvw2U51Qrf5TVlJIyphp6I24/o1xETW Ix0w== X-Received: by 10.68.216.161 with SMTP id or1mr16280771pbc.147.1371549198939; Tue, 18 Jun 2013 02:53:18 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id u6sm17520037pbb.46.2013.06.18.02.53.10 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Tue, 18 Jun 2013 02:53:17 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: qemu-devel@nongnu.org Date: Tue, 18 Jun 2013 19:47:06 +1000 Message-Id: <3146cc9b9a685f67264df4aefb55c1b1a1e2d4e4.1371548267.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.8.3.rc1.44.gb387c77.dirty In-Reply-To: References: X-Gm-Message-State: ALoCoQkKlnqYIQrOg3wkY8eyoZI54mF4iyA62Mr2/LPHLYD1F2DL3r01im524M9Pp1WBzYq9IMDI X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::22d Cc: peter.maydell@linaro.org, aliguori@us.ibm.com, mst@redhat.com, pbonzini@redhat.com, edgar.iglesias@gmail.com, afaerber@suse.de Subject: [Qemu-devel] [RFC PATCH v1 5/7] target-arm: Remove ARMCPUClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite ARMCPUClass is only needed for super-class abstract function access. Just use Super classes for reset and realize access and remove ARMCPUClass completely. Signed-off-by: Peter Crosthwaite --- target-arm/cpu-qom.h | 20 -------------------- target-arm/cpu.c | 14 +++++--------- 2 files changed, 5 insertions(+), 29 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 12fcefe..c937cd7 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -24,28 +24,8 @@ #define TYPE_ARM_CPU "arm-cpu" -#define ARM_CPU_CLASS(klass) \ - OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU) #define ARM_CPU(obj) \ OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU) -#define ARM_CPU_GET_CLASS(obj) \ - OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU) - -/** - * ARMCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. - * - * An ARM CPU model. - */ -typedef struct ARMCPUClass { - /*< private >*/ - CPUClass parent_class; - /*< public >*/ - - DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); -} ARMCPUClass; /** * ARMCPU: diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 47a21ec..a64de0f 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -60,7 +60,7 @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) static void arm_cpu_reset(CPUState *s) { ARMCPU *cpu = ARM_CPU(s); - ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); + CPUClass *cc_super = CPU_GET_SUPER_CLASS(cpu, TYPE_ARM_CPU); CPUARMState *env = &cpu->env; if (qemu_loglevel_mask(CPU_LOG_RESET)) { @@ -68,7 +68,7 @@ static void arm_cpu_reset(CPUState *s) log_cpu_state(env, 0); } - acc->parent_reset(s); + cc_super->reset(s); memset(env, 0, offsetof(CPUARMState, breakpoints)); g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); @@ -158,7 +158,7 @@ static void arm_cpu_finalizefn(Object *obj) static void arm_cpu_realizefn(DeviceState *dev, Error **errp) { ARMCPU *cpu = ARM_CPU(dev); - ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); + DeviceClass *dc_super = DEVICE_GET_SUPER_CLASS(dev, TYPE_ARM_CPU); CPUARMState *env = &cpu->env; /* Some features automatically imply others: */ @@ -207,7 +207,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu_reset(CPU(cpu)); qemu_init_vcpu(env); - acc->parent_realize(dev, errp); + dc_super->realize(dev, errp); } /* CPU models */ @@ -802,14 +802,11 @@ static const ARMCPUInfo arm_cpus[] = { static void arm_cpu_class_init(ObjectClass *oc, void *data) { - ARMCPUClass *acc = ARM_CPU_CLASS(oc); - CPUClass *cc = CPU_CLASS(acc); + CPUClass *cc = CPU_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc); - acc->parent_realize = dc->realize; dc->realize = arm_cpu_realizefn; - acc->parent_reset = cc->reset; cc->reset = arm_cpu_reset; cc->class_by_name = arm_cpu_class_by_name; @@ -837,7 +834,6 @@ static const TypeInfo arm_cpu_type_info = { .instance_init = arm_cpu_initfn, .instance_finalize = arm_cpu_finalizefn, .abstract = true, - .class_size = sizeof(ARMCPUClass), .class_init = arm_cpu_class_init, };