Patchwork [RFC,v1,5/7] target-arm: Remove ARMCPUClass

login
register
mail settings
Submitter Peter Crosthwaite
Date June 18, 2013, 9:47 a.m.
Message ID <3146cc9b9a685f67264df4aefb55c1b1a1e2d4e4.1371548267.git.peter.crosthwaite@xilinx.com>
Download mbox | patch
Permalink /patch/252208/
State New
Headers show

Comments

Peter Crosthwaite - June 18, 2013, 9:47 a.m.
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

ARMCPUClass is only needed for super-class abstract function access.
Just use Super classes for reset and realize access and remove
ARMCPUClass completely.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 target-arm/cpu-qom.h | 20 --------------------
 target-arm/cpu.c     | 14 +++++---------
 2 files changed, 5 insertions(+), 29 deletions(-)

Patch

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 12fcefe..c937cd7 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -24,28 +24,8 @@ 
 
 #define TYPE_ARM_CPU "arm-cpu"
 
-#define ARM_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
 #define ARM_CPU(obj) \
     OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
-#define ARM_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
-
-/**
- * ARMCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
- *
- * An ARM CPU model.
- */
-typedef struct ARMCPUClass {
-    /*< private >*/
-    CPUClass parent_class;
-    /*< public >*/
-
-    DeviceRealize parent_realize;
-    void (*parent_reset)(CPUState *cpu);
-} ARMCPUClass;
 
 /**
  * ARMCPU:
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 47a21ec..a64de0f 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -60,7 +60,7 @@  static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
 static void arm_cpu_reset(CPUState *s)
 {
     ARMCPU *cpu = ARM_CPU(s);
-    ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
+    CPUClass *cc_super = CPU_GET_SUPER_CLASS(cpu, TYPE_ARM_CPU);
     CPUARMState *env = &cpu->env;
 
     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
@@ -68,7 +68,7 @@  static void arm_cpu_reset(CPUState *s)
         log_cpu_state(env, 0);
     }
 
-    acc->parent_reset(s);
+    cc_super->reset(s);
 
     memset(env, 0, offsetof(CPUARMState, breakpoints));
     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
@@ -158,7 +158,7 @@  static void arm_cpu_finalizefn(Object *obj)
 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     ARMCPU *cpu = ARM_CPU(dev);
-    ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
+    DeviceClass *dc_super = DEVICE_GET_SUPER_CLASS(dev, TYPE_ARM_CPU);
     CPUARMState *env = &cpu->env;
 
     /* Some features automatically imply others: */
@@ -207,7 +207,7 @@  static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     cpu_reset(CPU(cpu));
     qemu_init_vcpu(env);
 
-    acc->parent_realize(dev, errp);
+    dc_super->realize(dev, errp);
 }
 
 /* CPU models */
@@ -802,14 +802,11 @@  static const ARMCPUInfo arm_cpus[] = {
 
 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 {
-    ARMCPUClass *acc = ARM_CPU_CLASS(oc);
-    CPUClass *cc = CPU_CLASS(acc);
+    CPUClass *cc = CPU_CLASS(oc);
     DeviceClass *dc = DEVICE_CLASS(oc);
 
-    acc->parent_realize = dc->realize;
     dc->realize = arm_cpu_realizefn;
 
-    acc->parent_reset = cc->reset;
     cc->reset = arm_cpu_reset;
 
     cc->class_by_name = arm_cpu_class_by_name;
@@ -837,7 +834,6 @@  static const TypeInfo arm_cpu_type_info = {
     .instance_init = arm_cpu_initfn,
     .instance_finalize = arm_cpu_finalizefn,
     .abstract = true,
-    .class_size = sizeof(ARMCPUClass),
     .class_init = arm_cpu_class_init,
 };