From patchwork Mon Jun 17 22:39:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petar Jovanovic X-Patchwork-Id: 252070 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2B7B62C029B for ; Tue, 18 Jun 2013 08:41:55 +1000 (EST) Received: from localhost ([::1]:34379 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uoi7U-0001lB-Gr for incoming@patchwork.ozlabs.org; Mon, 17 Jun 2013 18:41:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34104) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uoi71-0001at-VG for qemu-devel@nongnu.org; Mon, 17 Jun 2013 18:41:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Uoi6x-0000Ov-Uy for qemu-devel@nongnu.org; Mon, 17 Jun 2013 18:41:23 -0400 Received: from multi.imgtec.com ([194.200.65.239]:49816) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uoi6x-0000Oc-PG for qemu-devel@nongnu.org; Mon, 17 Jun 2013 18:41:19 -0400 From: Petar Jovanovic To: Petar Jovanovic , "qemu-devel@nongnu.org" Thread-Topic: [PATCH] target-mips: fix mipsdsp_trunc16_sat16_round Thread-Index: AQHOVvGm2FzC3gTFVkmVSzHAMjLzoZksxYfngA3jV2c= Date: Mon, 17 Jun 2013 22:39:52 +0000 Message-ID: <56EA75BA695AE044ACFB41322F6D2BF4022320A1@BADAG02.ba.imgtec.org> References: <1369229701-87540-1-git-send-email-petar.jovanovic@rt-rk.com>, <56EA75BA695AE044ACFB41322F6D2BF402230260@BADAG02.ba.imgtec.org> In-Reply-To: <56EA75BA695AE044ACFB41322F6D2BF402230260@BADAG02.ba.imgtec.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.64.117] MIME-Version: 1.0 X-SEF-Processed: 7_3_0_01192__2013_06_17_23_41_17 X-detected-operating-system: by eggs.gnu.org: Windows XP X-Received-From: 194.200.65.239 Cc: "aurelien@aurel32.net" Subject: Re: [Qemu-devel] [PATCH] target-mips: fix mipsdsp_trunc16_sat16_round X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org ping diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 4116de9..306b332 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -648,16 +648,16 @@ static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a, uint16_t b, static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a, CPUMIPSState *env) { - int64_t temp; - - temp = (int32_t)a + 0x00008000; + uint16_t temp; - if (a > (int)0x7fff8000) { - temp = 0x7FFFFFFF; + if (a > 0x7FFF7FFF) { + temp = 0x7FFF; set_DSPControl_overflow_flag(1, 22, env); + } else { + temp = ((a + 0x8000) >> 16) & 0xFFFF; } - return (temp >> 16) & 0xFFFF; + return temp; } static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a, diff --git a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c index 3535b37..da6845b 100644 --- a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c +++ b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c @@ -12,18 +12,34 @@ int main() result = 0x12348765; __asm - ("precrq_rs.ph.w %0, %1, %2\n\t" + ("wrdsp $0\n\t" + "precrq_rs.ph.w %0, %1, %2\n\t" : "=r"(rd) : "r"(rs), "r"(rt) ); assert(result == rd); - rs = 0x7fffC678; + rs = 0x7FFFC678; rt = 0x865432A0; - result = 0x7fff8654; + result = 0x7FFF8654; __asm - ("precrq_rs.ph.w %0, %2, %3\n\t" + ("wrdsp $0\n\t" + "precrq_rs.ph.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(((dsp >> 22) & 0x01) == 1); + assert(result == rd); + + rs = 0xBEEFFEED; + rt = 0x7FFF8000; + result = 0xBEF07FFF; + + __asm + ("wrdsp $0\n\t" + "precrq_rs.ph.w %0, %2, %3\n\t" "rddsp %1\n\t" : "=r"(rd), "=r"(dsp) : "r"(rs), "r"(rt)