Patchwork [U-Boot] am33xx: fix the ddr_cmdtctrl structure

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Submitter Ilya Ledvich
Date June 17, 2013, 1:59 p.m.
Message ID <1371477567-8418-1-git-send-email-ilya@compulab.co.il>
Download mbox | patch
Permalink /patch/251901/
State Accepted
Delegated to: Tom Rini
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Comments

Ilya Ledvich - June 17, 2013, 1:59 p.m.
Fix the wrong mapping between the DDR I/O control registers on AM33XX
SoCs and the software representation in the SPL code.
The most recent public TRM defines the following DDR I/O control registers
offsets:
 * ddr_cmd0_ioctrl : offset 0x44E11404
 * ddr_cmd1_ioctrl : offset 0x44E11408
 * ddr_cmd2_ioctrl : offset 0x44E1140C
 * ddr_data0_ioctrl: offset 0x44E11440
 * ddr_data1_ioctrl: offset 0x44E11444

While the struct ddr_cmdtctrl has also some reserved bits in the beginning.
The struct is mapped to the address 0x44E11404. As a result "cm0ioctl" points
to the ddr_cmd1_ioctrl register, "cm1ioctl" to the ddr_cmd2_ioctrl and etc.
Registers ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because
of this mapping mismatch.

Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
---
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |    1 -
 1 file changed, 1 deletion(-)
Peter Korsgaard - June 17, 2013, 8:13 p.m.
>>>>> "Ilya" == Ilya Ledvich <ilya@compulab.co.il> writes:

 Ilya> Fix the wrong mapping between the DDR I/O control registers on
 Ilya> AM33XX SoCs and the software representation in the SPL code.  The
 Ilya> most recent public TRM defines the following DDR I/O control
 Ilya> registers offsets:

 Ilya>  * ddr_cmd0_ioctrl : offset 0x44E11404
 Ilya>  * ddr_cmd1_ioctrl : offset 0x44E11408
 Ilya>  * ddr_cmd2_ioctrl : offset 0x44E1140C
 Ilya>  * ddr_data0_ioctrl: offset 0x44E11440
 Ilya>  * ddr_data1_ioctrl: offset 0x44E11444

 Ilya> While the struct ddr_cmdtctrl has also some reserved bits in the
 Ilya> beginning.  The struct is mapped to the address 0x44E11404. As a
 Ilya> result "cm0ioctl" points to the ddr_cmd1_ioctrl register,
 Ilya> "cm1ioctl" to the ddr_cmd2_ioctrl and etc.  Registers
 Ilya> ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because
 Ilya> of this mapping mismatch.

 Ilya> Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>

Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
Tom Rini - July 2, 2013, 8:06 p.m.
On Mon, Jun 17, 2013 at 04:59:27PM +0300, Ilya Ledvich wrote:

> Fix the wrong mapping between the DDR I/O control registers on AM33XX
> SoCs and the software representation in the SPL code.
> The most recent public TRM defines the following DDR I/O control registers
> offsets:
>  * ddr_cmd0_ioctrl : offset 0x44E11404
>  * ddr_cmd1_ioctrl : offset 0x44E11408
>  * ddr_cmd2_ioctrl : offset 0x44E1140C
>  * ddr_data0_ioctrl: offset 0x44E11440
>  * ddr_data1_ioctrl: offset 0x44E11444
> 
> While the struct ddr_cmdtctrl has also some reserved bits in the beginning.
> The struct is mapped to the address 0x44E11404. As a result "cm0ioctl" points
> to the ddr_cmd1_ioctrl register, "cm1ioctl" to the ddr_cmd2_ioctrl and etc.
> Registers ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because
> of this mapping mismatch.
> 
> Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>

Applied to u-boot-ti/master, thanks!

Patch

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index fb4e78e..a529460 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -267,7 +267,6 @@  void config_ddr_data(const struct ddr_data *data, int nr);
  * This structure represents the DDR io control on AM33XX devices.
  */
 struct ddr_cmdtctrl {
-	unsigned int resv1[1];
 	unsigned int cm0ioctl;
 	unsigned int cm1ioctl;
 	unsigned int cm2ioctl;