From patchwork Mon Jun 17 12:06:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuo-Jung Su X-Patchwork-Id: 251830 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BE00B2C029E for ; Mon, 17 Jun 2013 22:09:43 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4B1D04A1DE; Mon, 17 Jun 2013 14:09:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Kf6+3IxWiaiv; Mon, 17 Jun 2013 14:09:28 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6794D4A1CB; Mon, 17 Jun 2013 14:08:22 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 150E84A1EC for ; Mon, 17 Jun 2013 14:08:16 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id adkPZAXT-7R9 for ; Mon, 17 Jun 2013 14:08:11 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f48.google.com (mail-pb0-f48.google.com [209.85.160.48]) by theia.denx.de (Postfix) with ESMTPS id 2E19B4A1BC for ; Mon, 17 Jun 2013 14:07:41 +0200 (CEST) Received: by mail-pb0-f48.google.com with SMTP id ma3so2693167pbc.21 for ; Mon, 17 Jun 2013 05:07:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references; bh=sVCU3inBJBBkt1n9vLHAgCFw3HyetkHzoRAxaPy0jIY=; b=Roy03GXvzH6QdybAeRyR3s/HY5tGA38rtpTEnKFHO5MoGPbLgj020Q9D98SKyp5Zyo bfK0qucxDDQA0BIi1Cq+/qvz1oiIG9M0pnA47vz1GxKuzXPyc8ZSyat/BdnPXczh4yNA DvmAwl7l/ceWvtHe/pewHe3eS+eKGGb0jldru4KE+G77n++j/z8FRFaviwB0XztdjDZJ +38zvBvH6Ht8/Gpy6fvcxDW7gelYNzuNkR5EeC5C6dsYUWGuMbF1+BeGoA/OqREwqk+M KkVKKUWY8z6ARrS463P//90pzSqryvpWqU/yUSC7vUjCBCsoB3y3BbkxO/46tF8TmByj detQ== X-Received: by 10.68.134.40 with SMTP id ph8mr12579574pbb.177.1371470858711; Mon, 17 Jun 2013 05:07:38 -0700 (PDT) Received: from localhost.localdomain (114-35-170-161.HINET-IP.hinet.net. [114.35.170.161]) by mx.google.com with ESMTPSA id wt5sm13621839pbc.38.2013.06.17.05.07.36 for (version=TLSv1 cipher=DES-CBC3-SHA bits=168/168); Mon, 17 Jun 2013 05:07:38 -0700 (PDT) From: Kuo-Jung Su To: u-boot@lists.denx.de Date: Mon, 17 Jun 2013 20:06:58 +0800 Message-Id: <1371470824-3228-9-git-send-email-dantesu@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1371470824-3228-1-git-send-email-dantesu@gmail.com> References: <1371470824-3228-1-git-send-email-dantesu@gmail.com> In-Reply-To: <1364540788-13943-1-git-send-email-dantesu@gmail.com> References: <1364540788-13943-1-git-send-email-dantesu@gmail.com> Cc: Kuo-Jung Su Subject: [U-Boot] [PATCH v5 08/14] arm: add Faraday processor core support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Kuo-Jung Su This adds i/d-cache control, mmu setup & bootstrap code for Faraday cores. Signed-off-by: Kuo-Jung Su CC: Albert Aribaud --- Changes for v5: - Initial commit which is separated from "arm: add Faraday common utilities" arch/arm/cpu/faraday/Makefile | 55 +++++ arch/arm/cpu/faraday/config.mk | 33 +++ arch/arm/cpu/faraday/cpu.c | 346 ++++++++++++++++++++++++++++++++ arch/arm/cpu/faraday/start.S | 431 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 865 insertions(+) create mode 100644 arch/arm/cpu/faraday/Makefile create mode 100644 arch/arm/cpu/faraday/config.mk create mode 100644 arch/arm/cpu/faraday/cpu.c create mode 100644 arch/arm/cpu/faraday/start.S -- 1.7.9.5 diff --git a/arch/arm/cpu/faraday/Makefile b/arch/arm/cpu/faraday/Makefile new file mode 100644 index 0000000..ecb240a --- /dev/null +++ b/arch/arm/cpu/faraday/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).o + +src-y := cpu.o + +START = start.o +COBJS = $(src-y) + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE +START := +endif +endif + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/faraday/config.mk b/arch/arm/cpu/faraday/config.mk new file mode 100644 index 0000000..f03030a --- /dev/null +++ b/arch/arm/cpu/faraday/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float + +PLATFORM_CPPFLAGS += -march=armv4 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/faraday/cpu.c b/arch/arm/cpu/faraday/cpu.c new file mode 100644 index 0000000..570b8b2 --- /dev/null +++ b/arch/arm/cpu/faraday/cpu.c @@ -0,0 +1,346 @@ +/* + * arch/arm/cpu/faraday/cpu.c + * + * (C) Copyright 2013 Faraday Technology + * Dante Su + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int cleanup_before_linux(void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + disable_interrupts(); + + /* turn off D-cache */ + dcache_disable(); + + /* flush I-cache */ + __asm__ __volatile__ ( + "mov r0, #0\n" + "mcr p15, 0, r0, c7, c5, 0\n" /* invalidate i-cache all */ + : /* output */ + : /* input */ + : "r0" /* clobber list */ + ); + + return 0; +} + +/* + * This arch_preboot_os() overrides the weak function + * in "cmd_bootm.c". + */ +void arch_preboot_os(void) +{ + cleanup_before_linux(); +} + +#ifdef CONFIG_SYS_DCACHE_OFF + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +#else + +void flush_dcache_all(void) +{ + __asm__ __volatile__ ( + "mov r0,#0\n" + "mcr p15,0,r0,c7,c14,0\n" /* clean & invalidate d-cache all */ + "mcr p15,0,r0,c7,c10,4\n" /* drain write buffer */ + : /* output */ + : /* input */ + : "r0" /* clobber list */ + ); +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + unsigned long align = CONFIG_SYS_CACHELINE_SIZE; + unsigned long mask = ~(align - 1); + + /* aligned to cache line */ + stop = (stop + (align - 1)) & mask; + start = start & mask; + + __asm__ __volatile__ ( + "1:\n" + "mcr p15,0,%0,c7,c14,1\n" /* clean & invalidate d-cache line */ + "add %0,%0,%2\n" + "cmp %0,%1\n" + "blo 1b\n" + "mov r0,#0\n" + "mcr p15,0,r0,c7,c10,4\n" /* drain write buffer */ + : "+r"(start) /* output */ + : "r"(stop), "r"(align) /* input */ + : "r0" /* clobber list */ + ); +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + unsigned long align = CONFIG_SYS_CACHELINE_SIZE; + unsigned long mask = ~(align - 1); + + /* aligned to cache line */ + stop = (stop + (align - 1)) & mask; + start = start & mask; + + __asm__ __volatile__ ( + "1:\n" + "mcr p15,0,%0,c7,c6,1\n" /* invalidate cache line */ + "add %0,%0,%2\n" + "cmp %0,%1\n" + "blo 1b\n" + : "+r"(start) /* output */ + : "r"(stop), "r"(align) /* input */ + ); +} + +void invalidate_dcache_all(void) +{ + __asm__ __volatile__ ( + "mov r0,#0\n" + "mcr p15,0,r0,c7,c6,0\n" /* invalidate d-cache all */ + : /* output */ + : /* input */ + : "r0"/* clobber list */ + ); +} + +void invalidate_icache_all(void) +{ + __asm__ __volatile__ ( + "mov r0,#0\n" + "mcr p15,0,r0,c7,c5,0\n" /* invalidate i-cache all */ + : /* output */ + : /* input */ + : "r0" /* clobber list */ + ); +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} + +#endif /* !defined(CONFIG_SYS_DCACHE_OFF) */ + +void enable_caches(void) +{ + icache_enable(); + +#if !defined(CONFIG_SYS_DCACHE_OFF) + if (gd->arch.cpu_mmu) { + puts("MMU: on\n"); + dcache_enable(); + } else +#endif + puts("MMU: off\n"); +} + +#define CPUID_VID(x) (((x) >> 24) & 0xff) +#define CPUID_ISA(x) (((x) >> 16) & 0xff) +#define CPUID_PID(x) (((x) >> 4) & 0x0fff) +#define CPUID_REV(x) ((x) & 0x0f) /* revision */ +#define CPUID_NOREV(x) (((x) >> 4) & 0x0fffffff) + +/* Vendor ID */ +#define CPUID_VID_ARM 0x41 +#define CPUID_VID_FARADAY 0x66 + +/* Instruction Set Architecture */ +#define CPUID_ISA_ARMV4 0x01 +#define CPUID_ISA_ARMV5TE 0x05 +#define CPUID_ISA_ARMV5TEJ 0x06 + +/* Faraday ARMv4 cores */ +#define CPUID_FA526 0x6601526 +#define CPUID_FA626 0x6601626 + +/* Faraday ARMv5TE cores */ +#define CPUID_FA606TE 0x6605606 +#define CPUID_FA616TE 0x6605616 +#define CPUID_FA626TE 0x6605626 +#define CPUID_FA726TE 0x6605726 + +#ifdef CONFIG_ARCH_CPU_INIT + +int arch_cpu_init(void) +{ + unsigned int id, ctr; + + __asm__ __volatile__ ( + "mrc p15, 0, %0, c0, c0, 0\n" + "mrc p15, 0, %1, c0, c0, 1\n" + : "=r"(id), "=r"(ctr) /* output */ + : /* input */ + ); + + gd->arch.cpu_id = id; + + /* MMU/D-Cache */ + switch (CPUID_NOREV(gd->arch.cpu_id)) { + case CPUID_FA606TE: /* FA606TE (no-mmu) */ + /* Disable MMU/D-Cache */ + gd->arch.cpu_mmu = 0; + break; + default: + /* Enable MMU/D-Cache */ + gd->arch.cpu_mmu = 1; + break; + } + + return 0; +} +#endif /* #ifdef CONFIG_ARCH_CPU_INIT */ + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + char cpu_name[32]; + uint vid = CPUID_VID(gd->arch.cpu_id); + uint pid = CPUID_PID(gd->arch.cpu_id); + + /* build cpu_name */ + switch (vid) { + case CPUID_VID_FARADAY: /* Faraday */ + switch (CPUID_ISA(gd->arch.cpu_id)) { + case CPUID_ISA_ARMV5TE: + sprintf(cpu_name, "FA%xTE", pid); + break; + default: + sprintf(cpu_name, "FA%x", pid); + break; + } + break; + case CPUID_VID_ARM: /* ARM */ + if ((pid & 0xff0) == 0xc00) + sprintf(cpu_name, "Cortex-A%u", (pid & 0x00f)); + else if (pid >= 0xa00) + sprintf(cpu_name, "ARM%x", 0x1000 + (pid - 0xa00)); + else + sprintf(cpu_name, "ARM%x", pid); + break; + default: + sprintf(cpu_name, "Unknown"); + break; + } + + /* print cpu_info */ + printf("CPU: %s %u MHz\n", + cpu_name, (unsigned int)(clock_get_rate(CPU_CLK) / 1000000)); + + printf("AHB: %u MHz\n", + (unsigned int)(clock_get_rate(AHB_CLK) / 1000000)); + + printf("APB: %u MHz\n", + (unsigned int)(clock_get_rate(APB_CLK) / 1000000)); + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +#ifndef CONFIG_SYS_DCACHE_OFF + +#undef CACHE_SETUP +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) +#define CACHE_SETUP DCACHE_WRITETHROUGH +#else +#define CACHE_SETUP DCACHE_WRITEBACK +#endif + +#ifdef CONFIG_USE_IRQ +static u32 page_table[256] __aligned(1024); +#endif + +/* + * This dram_bank_mmu_setup() overrides the weak function + * in "cache-cp15.c". + */ +void dram_bank_mmu_setup(int bank) +{ + u32 pa, *sect_table = (u32 *)gd->arch.tlb_addr; + bd_t *bd = gd->bd; + int i; + + for (i = bd->bi_dram[bank].start >> 20; + i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; + i++) { + pa = i << 20; + sect_table[i] = pa | (3 << 10) | CACHE_SETUP; + } + +#ifdef CONFIG_USE_IRQ + /* only setup exception table when bank == 0 */ + if (bank) + return; + + /* make sure the exception table is mapped to 0x00000000 */ + sect_table[0] = (u32)page_table | 0x11; /* coarse page */ + page_table[0] = gd->relocaddr | 0xff2; /* small page (4KB) */ + + __asm__ __volatile__ ( + "mov r0, #0\n" + "mcr p15, 0, r0, c8, c7, 0\n" /* invalidate TLB */ + "mcr p15, 0, r0, c7, c5, 0\n" /* invalidate I Cache */ + : /* output */ + : /* input */ + : "r0" /* clobber list */ + ); +#endif /* CONFIG_USE_IRQ */ +} +#endif /* !CONFIG_SYS_DCACHE_OFF */ + +void reset_cpu(unsigned long ignored) +{ +#ifdef CONFIG_FTWDT010_BASE + struct ftwdt010_wdt __iomem *regs = + (struct ftwdt010_wdt __iomem *)CONFIG_FTWDT010_BASE; + + /* Disable WDT */ + writel(0, ®s->wdcr); + /* Timeout in 1000 ticks */ + writel(1000, ®s->wdload); + /* Enable WDT with System Reset Function */ + writel(FTWDT010_WDCR_ENABLE | FTWDT010_WDCR_RST, ®s->wdcr); + /* Kick it to make sure it's in running state */ + writel(FTWDT010_WDRESTART_MAGIC, ®s->wdrestart); +#endif +} diff --git a/arch/arm/cpu/faraday/start.S b/arch/arm/cpu/faraday/start.S new file mode 100644 index 0000000..916b4a2 --- /dev/null +++ b/arch/arm/cpu/faraday/start.S @@ -0,0 +1,431 @@ +/* + * u-boot - Startup Code for Faraday CPU-core + * + * Base is arch/arm/cpu/arm926ejs/start.S + * + * (C) Copyright 2013 Faraday Technology + * Dante Su + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG +.globl _start +_start: +.globl _NOR_BOOT_CFG +_NOR_BOOT_CFG: + .word CONFIG_SYS_DV_NOR_BOOT_CFG + b reset +#else +.globl _start +_start: + b reset +#endif +#ifdef CONFIG_SPL_BUILD +/* No exception handlers in preloader */ + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang +/* pad to 64 byte boundary */ + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 +#else + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: + .word undefined_instruction +_software_interrupt: + .word software_interrupt +_prefetch_abort: + .word prefetch_abort +_data_abort: + .word data_abort +_not_used: + .word not_used +_irq: + .word irq +_fiq: + .word fiq + +#endif /* CONFIG_SPL_BUILD */ + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +.globl _TEXT_BASE +_TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else + .word CONFIG_SYS_TEXT_BASE +#endif + +/* + * These are defined in the board-specific linker script. + * Subtracting _start from them lets the linker put their + * relative position in the executable instead of leaving + * them null. + */ +.globl _bss_start_ofs +_bss_start_ofs: + .word __bss_start - _start + +.globl _bss_end_ofs +_bss_end_ofs: + .word __bss_end - _start + +.globl _end_ofs +_end_ofs: + .word _end - _start + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + + /* + * Relocate U-Boot to RAM + * It's copied from the old u-boot release. + */ +#ifndef CONFIG_SPL_BUILD + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + teq r0, r1 /* don't reloc during debug */ + bleq rr_exit + ldr r2, _end_ofs /* r2 <- size of u-boot */ + add r2, r0, r2 /* r2 <- source end address */ + +rr_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + blo rr_loop + + /* Adjust the pc to use the correct text address */ + adr r0, _start + ldr r1, _TEXT_BASE + sub r2, pc, r0 + add r2, r2, #4 + add pc, r1, r2 + +rr_exit: +#endif /* !CONFIG_SPL_BUILD */ + + bl _main + +/*---------------------------------------------------------------------------*/ + + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + bx lr + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + /* + * flush D cache before disabling it + */ + mov r0, #0 + mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ + mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + + /* + * disable MMU and D cache + * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ +#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH + orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ +#else + bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ +#endif + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ +#ifndef CONFIG_SYS_ICACHE_OFF + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ +#endif + mcr p15, 0, r0, c1, c0, 0 + + /* + * Go setup Memory and board specific bits prior to relocation. + */ + mov ip, lr /* perserve link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +#ifndef CONFIG_SPL_BUILD +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + @ carve out a frame on current user stack + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + ldr r2, IRQ_STACK_START_IN + @ get values for "aborted" pc and cpsr (into parm regs) + ldmia r2, {r2 - r3} + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, IRQ_STACK_START_IN @ setup our mode stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm +#endif /* CONFIG_SPL_BUILD */ + +/* + * exception handlers + */ +#ifdef CONFIG_SPL_BUILD + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* switch to abort stack */ +1: + bl 1b /* hang and never return */ +#else /* !CONFIG_SPL_BUILD */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif +#endif /* CONFIG_SPL_BUILD */