From patchwork Sat Jun 15 09:03:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 251604 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 95E122C05FD for ; Sat, 15 Jun 2013 19:27:04 +1000 (EST) Received: from e9.ny.us.ibm.com (e9.ny.us.ibm.com [32.97.182.139]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "e9.ny.us.ibm.com", Issuer "GeoTrust SSL CA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id E8F832C009E for ; Sat, 15 Jun 2013 19:03:38 +1000 (EST) Received: from /spool/local by e9.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Sat, 15 Jun 2013 05:03:35 -0400 Received: from d01relay01.pok.ibm.com (d01relay01.pok.ibm.com [9.56.227.233]) by d01dlp01.pok.ibm.com (Postfix) with ESMTP id B7BF838C801A for ; Sat, 15 Jun 2013 05:03:33 -0400 (EDT) Received: from d01av02.pok.ibm.com (d01av02.pok.ibm.com [9.56.224.216]) by d01relay01.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r5F93YqB305718 for ; Sat, 15 Jun 2013 05:03:34 -0400 Received: from d01av02.pok.ibm.com (loopback [127.0.0.1]) by d01av02.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r5F93X1m026320 for ; Sat, 15 Jun 2013 06:03:33 -0300 Received: from shangw ([9.125.26.179]) by d01av02.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id r5F93OsK025830; Sat, 15 Jun 2013 06:03:33 -0300 Received: by shangw (Postfix, from userid 1000) id 5521B3019B5; Sat, 15 Jun 2013 17:03:32 +0800 (CST) From: Gavin Shan To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 20/27] powerpc/eeh: Enable EEH check for config access Date: Sat, 15 Jun 2013 17:03:11 +0800 Message-Id: <1371286998-2842-21-git-send-email-shangw@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1371286998-2842-1-git-send-email-shangw@linux.vnet.ibm.com> References: <1371286998-2842-1-git-send-email-shangw@linux.vnet.ibm.com> X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13061509-7182-0000-0000-000007584E47 Cc: Gavin Shan X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The patch enables EEH check and let EEH core to process the EEH errors for PowerNV platform while accessing config space. Originally, the implementation already had mechanism to check EEH errors and tried to recover from them. However, we never let EEH core to handle the EEH errors. Signed-off-by: Gavin Shan --- arch/powerpc/platforms/powernv/pci.c | 40 +++++++++++++++++++++++++++++++++- 1 files changed, 39 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c index 20af220..6d9a506 100644 --- a/arch/powerpc/platforms/powernv/pci.c +++ b/arch/powerpc/platforms/powernv/pci.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include #include "powernv.h" #include "pci.h" @@ -259,6 +261,10 @@ static int pnv_pci_read_config(struct pci_bus *bus, { struct pci_controller *hose = pci_bus_to_host(bus); struct pnv_phb *phb = hose->private_data; +#ifdef CONFIG_EEH + struct device_node *busdn, *dn; + struct eeh_pe *phb_pe = NULL; +#endif u32 bdfn = (((uint64_t)bus->number) << 8) | devfn; s64 rc; @@ -291,8 +297,34 @@ static int pnv_pci_read_config(struct pci_bus *bus, cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n", bus->number, devfn, where, size, *val); - /* Check if the PHB got frozen due to an error (no response) */ + /* + * Check if the specified PE has been put into frozen + * state. On the other hand, we needn't do that while + * the PHB has been put into frozen state because of + * PHB-fatal errors. + */ +#ifdef CONFIG_EEH + phb_pe = eeh_phb_pe_get(hose); + if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED)) + return PCIBIOS_SUCCESSFUL; + + if (phb->eeh_enabled) { + if (*val == EEH_IO_ERROR_VALUE(size)) { + busdn = pci_bus_to_OF_node(bus); + for (dn = busdn->child; dn; dn = dn->sibling) { + struct pci_dn *pdn = PCI_DN(dn); + + if (pdn && pdn->devfn == devfn && + eeh_dev_check_failure(of_node_to_eeh_dev(dn))) + return PCIBIOS_DEVICE_NOT_FOUND; + } + } + } else { + pnv_pci_config_check_eeh(phb, bus, bdfn); + } +#else pnv_pci_config_check_eeh(phb, bus, bdfn); +#endif return PCIBIOS_SUCCESSFUL; } @@ -323,8 +355,14 @@ static int pnv_pci_write_config(struct pci_bus *bus, default: return PCIBIOS_FUNC_NOT_SUPPORTED; } + /* Check if the PHB got frozen due to an error (no response) */ +#ifdef CONFIG_EEH + if (!phb->eeh_enabled) + pnv_pci_config_check_eeh(phb, bus, bdfn); +#else pnv_pci_config_check_eeh(phb, bus, bdfn); +#endif return PCIBIOS_SUCCESSFUL; }