From patchwork Fri Jun 14 16:37:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 251464 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A39522C008E for ; Sat, 15 Jun 2013 02:39:24 +1000 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UnX1A-0001gT-OU; Fri, 14 Jun 2013 16:38:29 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UnX12-0003yV-96; Fri, 14 Jun 2013 16:38:20 +0000 Received: from avon.wwwdotorg.org ([2001:470:1f0f:bd7::2]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UnX0p-0003vy-BD for linux-arm-kernel@lists.infradead.org; Fri, 14 Jun 2013 16:38:08 +0000 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id EDFEF6413; Fri, 14 Jun 2013 10:46:12 -0600 (MDT) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 39ED8E47A6; Fri, 14 Jun 2013 10:37:29 -0600 (MDT) From: Stephen Warren To: arm@kernel.org Subject: [GIT PULL 4/5] ARM: tegra: core SoC support enhancements Date: Fri, 14 Jun 2013 10:37:17 -0600 Message-Id: <1371227838-18764-5-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1371227838-18764-1-git-send-email-swarren@wwwdotorg.org> References: <1371227838-18764-1-git-send-email-swarren@wwwdotorg.org> X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.97.7 at avon.wwwdotorg.org X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130614_123807_509148_AAD6AA0E X-CRM114-Status: GOOD ( 10.00 ) X-Spam-Score: -2.2 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.3 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stephen Warren X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org This branch contains fixes and enhancement for core Tegra Soc support: * CPU hotplug support for Tegra114. * Some preliminary work on Tegra114 CPU sleep modes. * Minor fix for EMC table DT parsing. This branch is based on v3.10-rc1. ---------------------------------------------------------------- The following changes since commit f722406faae2d073cc1d01063d1123c35425939e: Linux 3.10-rc1 are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git tegra-for-3.11-soc for you to fetch changes up to 8f6a0b6528820f9efec36e5843181cc178fa9de8: ARM: tegra: don't pass CPU ID to tegra_{set,clear}_cpu_in_lp2 ---------------------------------------------------------------- Dmitry Osipenko (1): ARM: tegra: emc: correction of ram-code parsing from dt Joseph Lo (12): ARM: tegra: add an assembly marco to check Tegra SoC ID ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9 ARM: tegra: make tegra_resume can work for Tegra114 ARM: tegra114: add power up sequence for warm boot CPU clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_ops ARM: tegra114: add CPU hotplug support ARM: tegra: add cpu_disable for hotplug ARM: tegra: remove ifdef in the tegra_resume ARM: tegra: cpuidle: move the init function behind the suspend init function ARM: tegra: hook tegra_tear_down_cpu function in the PM suspend init function ARM: tegra: cpuidle: using IS_ENABLED for multi SoCs management in init func ARM: tegra: don't pass CPU ID to tegra_{set,clear}_cpu_in_lp2 arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/common.c | 2 ++ arch/arm/mach-tegra/common.h | 1 + arch/arm/mach-tegra/cpuidle-tegra20.c | 10 ++---- arch/arm/mach-tegra/cpuidle-tegra30.c | 10 ++---- arch/arm/mach-tegra/cpuidle.c | 19 ++++------- arch/arm/mach-tegra/cpuidle.h | 15 ++------- arch/arm/mach-tegra/flowctrl.h | 1 + arch/arm/mach-tegra/fuse.h | 22 +++++++------ arch/arm/mach-tegra/hotplug.c | 13 ++++++++ arch/arm/mach-tegra/platsmp.c | 26 ++++++++++++++- arch/arm/mach-tegra/pm.c | 25 ++++++++++++--- arch/arm/mach-tegra/pm.h | 4 +-- arch/arm/mach-tegra/reset-handler.S | 51 ++++++++++++++++-------------- arch/arm/mach-tegra/sleep-tegra30.S | 30 +++++++++++++++--- arch/arm/mach-tegra/sleep.S | 8 +++-- arch/arm/mach-tegra/sleep.h | 35 ++++++++++++++++---- arch/arm/mach-tegra/tegra2_emc.c | 2 +- drivers/clk/tegra/clk-tegra114.c | 23 +++++++++++++- 19 files changed, 204 insertions(+), 94 deletions(-)