diff mbox

[U-Boot,3/3] arm: omap3: Add SPL support to cm_t35

Message ID 1371200101-11510-3-git-send-email-sr@denx.de
State Changes Requested
Delegated to: Tom Rini
Headers show

Commit Message

Stefan Roese June 14, 2013, 8:55 a.m. UTC 
Add SPL U-Boot support to replace x-loader on the Compulab cm_t35
board. Currently only the 256MiB SDRAM board versions are supported.

Tested by booting via MMC and NAND.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
---
 board/compulab/cm_t35/cm_t35.c | 18 +++++++++++-
 include/configs/cm_t35.h       | 64 ++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 79 insertions(+), 3 deletions(-)

Comments

Igor Grinberg June 17, 2013, 11:53 a.m. UTC | #1 
Hi Stefan,

On 06/14/13 11:55, Stefan Roese wrote:
> Add SPL U-Boot support to replace x-loader on the Compulab cm_t35
> board. Currently only the 256MiB SDRAM board versions are supported.
> 
> Tested by booting via MMC and NAND.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Tom Rini <trini@ti.com>
> Cc: Igor Grinberg <grinberg@compulab.co.il>
> ---
>  board/compulab/cm_t35/cm_t35.c | 18 +++++++++++-
>  include/configs/cm_t35.h       | 64 ++++++++++++++++++++++++++++++++++++++++--
>  2 files changed, 79 insertions(+), 3 deletions(-)
> 
> diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
> index b0b80e5..cd7882e 100644
> --- a/board/compulab/cm_t35/cm_t35.c
> +++ b/board/compulab/cm_t35/cm_t35.c
> @@ -120,6 +120,22 @@ static inline int splash_load_from_nand(void)
>  }
>  #endif /* CONFIG_CMD_NAND */
>  
> +#ifdef CONFIG_SPL_BUILD
> +/*
> + * Routine: get_board_mem_timings
> + * Description: If we use SPL then there is no x-loader nor config header
> + * so we have to setup the DDR timings ourself on both banks.
> + */
> +void get_board_mem_timings(struct board_sdrc_timings *timings)
> +{
> +	timings->mr = MICRON_V_MR_165;
> +	timings->mcfg = MICRON_V_MCFG_165(256 << 20);
> +	timings->ctrla = MICRON_V_ACTIMA_165;
> +	timings->ctrlb = MICRON_V_ACTIMB_165;
> +	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +}
> +#endif

I still haven't checked the timings...
Hopefully, I will sometime during this week.

> +
>  int board_splash_screen_prepare(void)
>  {
>  	char *env_splashimage_value;
> @@ -443,7 +459,7 @@ void set_muxconf_regs(void)
>  		cm_t3730_set_muxconf();
>  }
>  
> -#ifdef CONFIG_GENERIC_MMC
> +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
>  int board_mmc_getcd(struct mmc *mmc)
>  {
>  	u8 val;
> diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
> index c6e357a..b76810d 100644
> --- a/include/configs/cm_t35.h
> +++ b/include/configs/cm_t35.h
> @@ -40,8 +40,6 @@
>  #define CONFIG_OMAP_GPIO
>  #define CONFIG_CM_T3X	/* working with CM-T35 and CM-T3730 */
>  
> -#define CONFIG_SYS_TEXT_BASE	0x80008000
> -
>  #define CONFIG_SDRC	/* The chip has SDRC controller */
>  
>  #include <asm/arch/cpu.h>		/* get chip and board defs */
> @@ -341,4 +339,66 @@
>  #define CONFIG_BMP_16BPP
>  #define CONFIG_SPLASH_SCREEN_PREPARE
>  
> +/* Defines for SPL */
> +#define CONFIG_SPL
> +#define CONFIG_SPL_FRAMEWORK
> +#define CONFIG_SPL_NAND_SIMPLE
> +#define CONFIG_SPL_TEXT_BASE		0x40200800
> +#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
> +#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
> +
> +#define CONFIG_SPL_BSS_START_ADDR	0x80000000
> +#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
> +
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
> +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
> +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
> +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
> +
> +#define CONFIG_SPL_BOARD_INIT
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBDISK_SUPPORT
> +#define CONFIG_SPL_I2C_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SPL_FAT_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SPL_NAND_SUPPORT
> +#define CONFIG_SPL_NAND_BASE
> +#define CONFIG_SPL_NAND_DRIVERS
> +#define CONFIG_SPL_NAND_ECC
> +#define CONFIG_SPL_GPIO_SUPPORT
> +#define CONFIG_SPL_POWER_SUPPORT
> +#define CONFIG_SPL_OMAP3_ID_NAND
> +#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
> +
> +/* NAND boot config */
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_PAGE_COUNT	64
> +#define CONFIG_SYS_NAND_PAGE_SIZE	2048
> +#define CONFIG_SYS_NAND_OOBSIZE		64
> +#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
> +#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
> +/*
> + * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
> + * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
> + */
> +#define CONFIG_SYS_NAND_ECCPOS		{ 1, 2, 3, 4, 5, 6, 7, 8, 9, \
> +					 10, 11, 12 }
> +#define CONFIG_SYS_NAND_ECCSIZE		512
> +#define CONFIG_SYS_NAND_ECCBYTES	3
> +
> +#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
> +
> +/*
> + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
> + * 64 bytes before this address should be set aside for u-boot.img's
> + * header. That is 0x800FFFC0--0x80100000 should not be used for any
> + * other needs.
> + */
> +#define CONFIG_SYS_TEXT_BASE		0x80100000

Now this is a problem.
This breaks the backward compatibility with our X-Loader and we
cannot just switch to 80100000...

> +#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
> +
>  #endif /* __CONFIG_H */
>
Tom Rini June 17, 2013, 12:38 p.m. UTC | #2 
On Mon, Jun 17, 2013 at 02:53:27PM +0300, Igor Grinberg wrote:
> Hi Stefan,
> 
> On 06/14/13 11:55, Stefan Roese wrote:
> > Add SPL U-Boot support to replace x-loader on the Compulab cm_t35
> > board. Currently only the 256MiB SDRAM board versions are supported.
> > 
> > Tested by booting via MMC and NAND.
> > 
> > Signed-off-by: Stefan Roese <sr@denx.de>
> > Cc: Tom Rini <trini@ti.com>
> > Cc: Igor Grinberg <grinberg@compulab.co.il>
[snip]
> > +/*
> > + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
> > + * 64 bytes before this address should be set aside for u-boot.img's
> > + * header. That is 0x800FFFC0--0x80100000 should not be used for any
> > + * other needs.
> > + */
> > +#define CONFIG_SYS_TEXT_BASE		0x80100000
> 
> Now this is a problem.
> This breaks the backward compatibility with our X-Loader and we
> cannot just switch to 80100000...

And thinking back to when I was doing more OMAP3 conversions, there's no
requirement to break compatibility with x-loader either.  You just need
to take care where you place things, see doc/SPL/README.omap3 for the
SPL and X-Loader compatible setup.
Igor Grinberg June 17, 2013, 1:38 p.m. UTC | #3 
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Hash: SHA1

On 06/17/13 15:38, Tom Rini wrote:
> On Mon, Jun 17, 2013 at 02:53:27PM +0300, Igor Grinberg wrote:
>> Hi Stefan,
>>
>> On 06/14/13 11:55, Stefan Roese wrote:
>>> Add SPL U-Boot support to replace x-loader on the Compulab cm_t35
>>> board. Currently only the 256MiB SDRAM board versions are supported.
>>>
>>> Tested by booting via MMC and NAND.
>>>
>>> Signed-off-by: Stefan Roese <sr@denx.de>
>>> Cc: Tom Rini <trini@ti.com>
>>> Cc: Igor Grinberg <grinberg@compulab.co.il>
> [snip]
>>> +/*
>>> + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
>>> + * 64 bytes before this address should be set aside for u-boot.img's
>>> + * header. That is 0x800FFFC0--0x80100000 should not be used for any
>>> + * other needs.
>>> + */
>>> +#define CONFIG_SYS_TEXT_BASE		0x80100000
>>
>> Now this is a problem.
>> This breaks the backward compatibility with our X-Loader and we
>> cannot just switch to 80100000...
> 
> And thinking back to when I was doing more OMAP3 conversions, there's no
> requirement to break compatibility with x-loader either.  You just need
> to take care where you place things, see doc/SPL/README.omap3 for the
> SPL and X-Loader compatible setup.

Actually, I was thinking about adding a target in boards.cfg, but
if we can make both (X-Loader and SPL) live in piece, then IMO,
we should go for it.

Thanks for the pointer!


- -- 
Regards,
Igor.
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Stefan Roese June 17, 2013, 1:52 p.m. UTC | #4 
On 17.06.2013 15:38, Igor Grinberg wrote:
>>>> +/*
>>>> + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
>>>> + * 64 bytes before this address should be set aside for u-boot.img's
>>>> + * header. That is 0x800FFFC0--0x80100000 should not be used for any
>>>> + * other needs.
>>>> + */
>>>> +#define CONFIG_SYS_TEXT_BASE		0x80100000
>>>
>>> Now this is a problem.
>>> This breaks the backward compatibility with our X-Loader and we
>>> cannot just switch to 80100000...
>>
>> And thinking back to when I was doing more OMAP3 conversions, there's no
>> requirement to break compatibility with x-loader either.  You just need
>> to take care where you place things, see doc/SPL/README.omap3 for the
>> SPL and X-Loader compatible setup.
> 
> Actually, I was thinking about adding a target in boards.cfg, but
> if we can make both (X-Loader and SPL) live in piece, then IMO,
> we should go for it.

I just did a quick check with moving CONFIG_SYS_TEXT_BASE back to
0x80008000 and CONFIG_SPL_BSS_START_ADDR up to 0x80100000. Seems to work
just fine.

I'll submit a new version in a short while.

Thanks,
Stefan
diff mbox

Patch

diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index b0b80e5..cd7882e 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -120,6 +120,22 @@  static inline int splash_load_from_nand(void)
 }
 #endif /* CONFIG_CMD_NAND */
 
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+	timings->mr = MICRON_V_MR_165;
+	timings->mcfg = MICRON_V_MCFG_165(256 << 20);
+	timings->ctrla = MICRON_V_ACTIMA_165;
+	timings->ctrlb = MICRON_V_ACTIMB_165;
+	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+}
+#endif
+
 int board_splash_screen_prepare(void)
 {
 	char *env_splashimage_value;
@@ -443,7 +459,7 @@  void set_muxconf_regs(void)
 		cm_t3730_set_muxconf();
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_getcd(struct mmc *mmc)
 {
 	u8 val;
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index c6e357a..b76810d 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -40,8 +40,6 @@ 
 #define CONFIG_OMAP_GPIO
 #define CONFIG_CM_T3X	/* working with CM-T35 and CM-T3730 */
 
-#define CONFIG_SYS_TEXT_BASE	0x80008000
-
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
@@ -341,4 +339,66 @@ 
 #define CONFIG_BMP_16BPP
 #define CONFIG_SPLASH_SCREEN_PREPARE
 
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+/*
+ * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
+ * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
+ */
+#define CONFIG_SYS_NAND_ECCPOS		{ 1, 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12 }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
 #endif /* __CONFIG_H */