From patchwork Fri Jun 14 06:49:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hu Tao X-Patchwork-Id: 251235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A0EEE2C0085 for ; Fri, 14 Jun 2013 16:51:13 +1000 (EST) Received: from localhost ([::1]:50691 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UnNqo-0000Xy-N6 for incoming@patchwork.ozlabs.org; Fri, 14 Jun 2013 02:51:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56529) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UnNqM-0000Xc-Nn for qemu-devel@nongnu.org; Fri, 14 Jun 2013 02:50:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UnNqL-0000iK-4G for qemu-devel@nongnu.org; Fri, 14 Jun 2013 02:50:42 -0400 Received: from [222.73.24.84] (port=27714 helo=song.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UnNqK-0000hM-MU for qemu-devel@nongnu.org; Fri, 14 Jun 2013 02:50:41 -0400 X-IronPort-AV: E=Sophos;i="4.87,863,1363104000"; d="scan'208";a="7545135" Received: from unknown (HELO tang.cn.fujitsu.com) ([10.167.250.3]) by song.cn.fujitsu.com with ESMTP; 14 Jun 2013 14:47:41 +0800 Received: from fnstmail02.fnst.cn.fujitsu.com (tang.cn.fujitsu.com [127.0.0.1]) by tang.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id r5E6oULQ026649 for ; Fri, 14 Jun 2013 14:50:33 +0800 Received: from G08FNSTD100614.fnst.cn.fujitsu.com ([10.167.233.156]) by fnstmail02.fnst.cn.fujitsu.com (Lotus Domino Release 8.5.3) with ESMTP id 2013061414483529-2124418 ; Fri, 14 Jun 2013 14:48:35 +0800 From: Hu Tao To: qemu-devel@nongnu.org Date: Fri, 14 Jun 2013 14:49:45 +0800 Message-Id: <1371192585-536-2-git-send-email-hutao@cn.fujitsu.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: <1371192585-536-1-git-send-email-hutao@cn.fujitsu.com> References: <1371192585-536-1-git-send-email-hutao@cn.fujitsu.com> X-MIMETrack: Itemize by SMTP Server on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/06/14 14:48:35, Serialize by Router on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/06/14 14:48:37, Serialize complete at 2013/06/14 14:48:37 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 222.73.24.84 Subject: [Qemu-devel] [PATCH 2/2] q35: use type-safe cast instead of directly access of parent dev X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org And remove variables if possible. Signed-off-by: Hu Tao --- hw/pci-host/q35.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 24df6b5..efe96d0 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -36,28 +36,26 @@ static int q35_host_init(SysBusDevice *dev) { - PCIBus *b; - PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev); - Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev); + PCIHostState *pci = PCI_HOST_BRIDGE(dev); + Q35PCIHost *s = Q35_HOST_DEVICE(dev); memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci, "pci-conf-idx", 4); sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); - sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); + sysbus_init_ioports(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci, "pci-conf-data", 4); sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); - sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4); + sysbus_init_ioports(dev, MCH_HOST_BRIDGE_CONFIG_DATA, 4); - if (pcie_host_init(&s->host) < 0) { + if (pcie_host_init(PCIE_HOST_BRIDGE(dev)) < 0) { return -1; } - b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", - s->mch.pci_address_space, s->mch.address_space_io, - 0, TYPE_PCIE_BUS); - s->host.pci.bus = b; - qdev_set_parent_bus(DEVICE(&s->mch), BUS(b)); + pci->bus = pci_bus_new(DEVICE(dev), "pcie.0", + s->mch.pci_address_space, s->mch.address_space_io, + 0, TYPE_PCIE_BUS); + qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); qdev_init_nofail(DEVICE(&s->mch)); return 0; @@ -105,9 +103,8 @@ static const TypeInfo q35_host_info = { static void mch_update_pciexbar(MCHPCIState *mch) { PCIDevice *pci_dev = &mch->d; - BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); + BusState *bus = qdev_get_parent_bus(DEVICE(pci_dev)); DeviceState *qdev = bus->parent; - Q35PCIHost *s = Q35_HOST_DEVICE(qdev); uint64_t pciexbar; int enable; @@ -139,18 +136,19 @@ static void mch_update_pciexbar(MCHPCIState *mch) break; } addr = pciexbar & addr_mask; - pcie_host_mmcfg_update(&s->host, enable, addr, length); + pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(qdev), enable, addr, length); } /* PAM */ static void mch_update_pam(MCHPCIState *mch) { + PCIDevice *pd = PCI_DEVICE(mch); int i; memory_region_transaction_begin(); for (i = 0; i < 13; i++) { pam_update(&mch->pam_regions[i], i, - mch->d.config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); + pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); } memory_region_transaction_commit(); } @@ -158,8 +156,10 @@ static void mch_update_pam(MCHPCIState *mch) /* SMRAM */ static void mch_update_smram(MCHPCIState *mch) { + PCIDevice *pd = PCI_DEVICE(mch); + memory_region_transaction_begin(); - smram_update(&mch->smram_region, mch->d.config[MCH_HOST_BRDIGE_SMRAM], + smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM], mch->smm_enabled); memory_region_transaction_commit(); } @@ -167,9 +167,10 @@ static void mch_update_smram(MCHPCIState *mch) static void mch_set_smm(int smm, void *arg) { MCHPCIState *mch = arg; + PCIDevice *pd = PCI_DEVICE(mch); memory_region_transaction_begin(); - smram_set_smm(&mch->smm_enabled, smm, mch->d.config[MCH_HOST_BRDIGE_SMRAM], + smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM], &mch->smram_region); memory_region_transaction_commit(); }