Message ID | 1371120709-18923-1-git-send-email-hutao@cn.fujitsu.com |
---|---|
State | New |
Headers | show |
Am 13.06.2013 12:51, schrieb Hu Tao: > Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> > --- > cputlb.c | 4 ++-- > hw/acpi/piix4.c | 6 +++--- > 2 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/cputlb.c b/cputlb.c > index 86666c8..1230e9e 100644 > --- a/cputlb.c > +++ b/cputlb.c > @@ -262,8 +262,8 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, > > #if defined(DEBUG_TLB) > printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx > - " prot=%x idx=%d pd=0x%08lx\n", > - vaddr, paddr, prot, mmu_idx, pd); > + " prot=%x idx=%d\n", > + vaddr, paddr, prot, mmu_idx); > #endif > > address = vaddr; > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > index e6525ac..eafa76f 100644 > --- a/hw/acpi/piix4.c > +++ b/hw/acpi/piix4.c > @@ -518,7 +518,7 @@ static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) > PIIX4PMState *s = opaque; > uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); > > - PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); > + PIIX4_DPRINTF("gpe read %lx == %x\n", addr, val); You need HWADDR_PRIx as seen below, because it might be %llx on some platforms. While touching it, changing %x to PRIx32 would be even better. > return val; > } > > @@ -530,7 +530,7 @@ static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, > acpi_gpe_ioport_writeb(&s->ar, addr, val); > pm_update_sci(s); > > - PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); > + PIIX4_DPRINTF("gpe write %lx <== %lu\n", addr, val); HWADDR_PRIx, PRIx64 Regards, Andreas > } > > static const MemoryRegionOps piix4_gpe_ops = { > @@ -579,7 +579,7 @@ static void pci_write(void *opaque, hwaddr addr, uint64_t data, > switch (addr) { > case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: > acpi_piix_eject_slot(opaque, (uint32_t)data); > - PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n", > + PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", > addr, data); > break; > default: >
Am 13.06.2013 13:10, schrieb Andreas Färber: > Am 13.06.2013 12:51, schrieb Hu Tao: >> Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> >> --- >> cputlb.c | 4 ++-- >> hw/acpi/piix4.c | 6 +++--- >> 2 files changed, 5 insertions(+), 5 deletions(-) >> >> diff --git a/cputlb.c b/cputlb.c >> index 86666c8..1230e9e 100644 >> --- a/cputlb.c >> +++ b/cputlb.c >> @@ -262,8 +262,8 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, >> >> #if defined(DEBUG_TLB) >> printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx >> - " prot=%x idx=%d pd=0x%08lx\n", >> - vaddr, paddr, prot, mmu_idx, pd); >> + " prot=%x idx=%d\n", >> + vaddr, paddr, prot, mmu_idx); >> #endif >> >> address = vaddr; >> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c >> index e6525ac..eafa76f 100644 >> --- a/hw/acpi/piix4.c >> +++ b/hw/acpi/piix4.c >> @@ -518,7 +518,7 @@ static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) >> PIIX4PMState *s = opaque; >> uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); >> >> - PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); >> + PIIX4_DPRINTF("gpe read %lx == %x\n", addr, val); > > You need HWADDR_PRIx as seen below, because it might be %llx on some > platforms. While touching it, changing %x to PRIx32 would be even better. > >> return val; >> } >> >> @@ -530,7 +530,7 @@ static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, >> acpi_gpe_ioport_writeb(&s->ar, addr, val); >> pm_update_sci(s); >> >> - PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); >> + PIIX4_DPRINTF("gpe write %lx <== %lu\n", addr, val); > > HWADDR_PRIx, PRIx64 err... PRIu64 obviously. > > Regards, > Andreas > >> } >> >> static const MemoryRegionOps piix4_gpe_ops = { >> @@ -579,7 +579,7 @@ static void pci_write(void *opaque, hwaddr addr, uint64_t data, >> switch (addr) { >> case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: >> acpi_piix_eject_slot(opaque, (uint32_t)data); >> - PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n", >> + PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", >> addr, data); >> break; >> default: >> > >
On Thu, Jun 13, 2013 at 01:10:04PM +0200, Andreas Färber wrote: > Am 13.06.2013 12:51, schrieb Hu Tao: > > Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> > > --- > > cputlb.c | 4 ++-- > > hw/acpi/piix4.c | 6 +++--- > > 2 files changed, 5 insertions(+), 5 deletions(-) > > > > diff --git a/cputlb.c b/cputlb.c > > index 86666c8..1230e9e 100644 > > --- a/cputlb.c > > +++ b/cputlb.c > > @@ -262,8 +262,8 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, > > > > #if defined(DEBUG_TLB) > > printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx > > - " prot=%x idx=%d pd=0x%08lx\n", > > - vaddr, paddr, prot, mmu_idx, pd); > > + " prot=%x idx=%d\n", > > + vaddr, paddr, prot, mmu_idx); > > #endif > > > > address = vaddr; > > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > > index e6525ac..eafa76f 100644 > > --- a/hw/acpi/piix4.c > > +++ b/hw/acpi/piix4.c > > @@ -518,7 +518,7 @@ static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) > > PIIX4PMState *s = opaque; > > uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); > > > > - PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); > > + PIIX4_DPRINTF("gpe read %lx == %x\n", addr, val); > > You need HWADDR_PRIx as seen below, because it might be %llx on some > platforms. While touching it, changing %x to PRIx32 would be even better. OK. Thanks! > > > return val; > > } > > > > @@ -530,7 +530,7 @@ static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, > > acpi_gpe_ioport_writeb(&s->ar, addr, val); > > pm_update_sci(s); > > > > - PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); > > + PIIX4_DPRINTF("gpe write %lx <== %lu\n", addr, val); > > HWADDR_PRIx, PRIx64 > > Regards, > Andreas > > > } > > > > static const MemoryRegionOps piix4_gpe_ops = { > > @@ -579,7 +579,7 @@ static void pci_write(void *opaque, hwaddr addr, uint64_t data, > > switch (addr) { > > case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: > > acpi_piix_eject_slot(opaque, (uint32_t)data); > > - PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n", > > + PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", > > addr, data); > > break; > > default: > > > > > -- > SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany > GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
diff --git a/cputlb.c b/cputlb.c index 86666c8..1230e9e 100644 --- a/cputlb.c +++ b/cputlb.c @@ -262,8 +262,8 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, #if defined(DEBUG_TLB) printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx - " prot=%x idx=%d pd=0x%08lx\n", - vaddr, paddr, prot, mmu_idx, pd); + " prot=%x idx=%d\n", + vaddr, paddr, prot, mmu_idx); #endif address = vaddr; diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index e6525ac..eafa76f 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -518,7 +518,7 @@ static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) PIIX4PMState *s = opaque; uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); - PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); + PIIX4_DPRINTF("gpe read %lx == %x\n", addr, val); return val; } @@ -530,7 +530,7 @@ static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, acpi_gpe_ioport_writeb(&s->ar, addr, val); pm_update_sci(s); - PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); + PIIX4_DPRINTF("gpe write %lx <== %lu\n", addr, val); } static const MemoryRegionOps piix4_gpe_ops = { @@ -579,7 +579,7 @@ static void pci_write(void *opaque, hwaddr addr, uint64_t data, switch (addr) { case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: acpi_piix_eject_slot(opaque, (uint32_t)data); - PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n", + PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, data); break; default:
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> --- cputlb.c | 4 ++-- hw/acpi/piix4.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-)