Patchwork [U-Boot,v2,05/10] ARM: highbank: set timer prescaler to 256

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Submitter Rob Herring
Date June 13, 2013, 3:24 a.m.
Message ID <1371093894-16424-5-git-send-email-robherring2@gmail.com>
Download mbox | patch
Permalink /patch/250962/
State Accepted
Delegated to: Albert ARIBAUD
Headers show

Comments

Rob Herring - June 13, 2013, 3:24 a.m.
From: Rob Herring <rob.herring@calxeda.com>

The 150MHz clock rate gives u-boot time functions problems and there's no
benefit to a fast clock, so lower the rate.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
---
v2: no change, resend

 arch/arm/cpu/armv7/highbank/timer.c        | 6 ++++--
 arch/arm/include/asm/arch-armv7/systimer.h | 2 ++
 2 files changed, 6 insertions(+), 2 deletions(-)

Patch

diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c
index da33d3c..d93de1e 100644
--- a/arch/arm/cpu/armv7/highbank/timer.c
+++ b/arch/arm/cpu/armv7/highbank/timer.c
@@ -26,7 +26,7 @@ 
 
 #undef SYSTIMER_BASE
 #define SYSTIMER_BASE		0xFFF34000	/* Timer 0 and 1 base	*/
-#define SYSTIMER_RATE		150000000
+#define SYSTIMER_RATE		(150000000 / 256)
 
 static ulong timestamp;
 static ulong lastinc;
@@ -40,9 +40,11 @@  int timer_init(void)
 	/*
 	 * Setup timer0
 	 */
+	writel(0, &systimer_base->timer0control);
 	writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
 	writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
-	writel(SYSTIMER_EN | SYSTIMER_32BIT, &systimer_base->timer0control);
+	writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256,
+		&systimer_base->timer0control);
 
 	reset_timer_masked();
 
diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h
index e745e37..08125f7 100644
--- a/arch/arm/include/asm/arch-armv7/systimer.h
+++ b/arch/arm/include/asm/arch-armv7/systimer.h
@@ -30,6 +30,8 @@ 
 #define SYSTIMER_RELOAD		0xFFFFFFFF
 #define SYSTIMER_EN		(1 << 7)
 #define SYSTIMER_32BIT		(1 << 1)
+#define SYSTIMER_PRESC_16	(1 << 2)
+#define SYSTIMER_PRESC_256	(1 << 3)
 
 struct systimer {
 	u32 timer0load;		/* 0x00 */