From patchwork Wed Jun 12 15:57:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 250834 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1A08B2C008F for ; Thu, 13 Jun 2013 02:33:55 +1000 (EST) Received: from localhost ([::1]:33291 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Umnzc-0004Al-65 for incoming@patchwork.ozlabs.org; Wed, 12 Jun 2013 12:33:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38439) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UmnzK-0004AK-Gy for qemu-devel@nongnu.org; Wed, 12 Jun 2013 12:33:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UmnzH-00038w-HF for qemu-devel@nongnu.org; Wed, 12 Jun 2013 12:33:34 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:57943 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UmnzH-00038k-8M for qemu-devel@nongnu.org; Wed, 12 Jun 2013 12:33:31 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1UmnQM-0002MJ-Ok; Wed, 12 Jun 2013 16:57:26 +0100 From: Peter Maydell To: Aurelien Jarno , Blue Swirl Date: Wed, 12 Jun 2013 16:57:21 +0100 Message-Id: <1371052645-9006-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1371052645-9006-1-git-send-email-peter.maydell@linaro.org> References: <1371052645-9006-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Anthony Liguori , Riku Voipio , Claudio Fontana , qemu-devel@nongnu.org Subject: [Qemu-devel] [PULL 09/13] tcg/aarch64: implement sign/zero extend operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Claudio Fontana implement the optional sign/zero extend operations with the dedicated aarch64 instructions. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Message-id: 51AC9A58.40502@huawei.com Signed-off-by: Peter Maydell --- tcg/aarch64/tcg-target.c | 58 ++++++++++++++++++++++++++++++++++++++++++++-- tcg/aarch64/tcg-target.h | 20 ++++++++-------- 2 files changed, 66 insertions(+), 12 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index ba65a62..934109e 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -674,6 +674,24 @@ static inline void tcg_out_rev16(TCGContext *s, int ext, TCGReg rd, TCGReg rm) tcg_out32(s, base | rm << 5 | rd); } +static inline void tcg_out_sxt(TCGContext *s, int ext, int s_bits, + TCGReg rd, TCGReg rn) +{ + /* using ALIASes SXTB 0x13001c00, SXTH 0x13003c00, SXTW 0x93407c00 + of SBFM Xd, Xn, #0, #7|15|31 */ + int bits = 8 * (1 << s_bits) - 1; + tcg_out_sbfm(s, ext, rd, rn, 0, bits); +} + +static inline void tcg_out_uxt(TCGContext *s, int s_bits, + TCGReg rd, TCGReg rn) +{ + /* using ALIASes UXTB 0x53001c00, UXTH 0x53003c00 + of UBFM Wd, Wn, #0, #7|15 */ + int bits = 8 * (1 << s_bits) - 1; + tcg_out_ubfm(s, 0, rd, rn, 0, bits); +} + #ifdef CONFIG_SOFTMMU #include "exec/softmmu_defs.h" @@ -721,8 +739,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) tcg_out_callr(s, TCG_REG_TMP); if (opc & 0x04) { /* sign extend */ - unsigned int bits = 8 * (1 << s_bits) - 1; - tcg_out_sbfm(s, 1, data_reg, TCG_REG_X0, 0, bits); /* 7|15|31 */ + tcg_out_sxt(s, 1, s_bits, data_reg, TCG_REG_X0); } else { tcg_out_movr(s, 1, data_reg, TCG_REG_X0); } @@ -1037,6 +1054,31 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_rev16(s, 0, args[0], args[1]); break; + case INDEX_op_ext8s_i64: + ext = 1; /* fall through */ + case INDEX_op_ext8s_i32: + tcg_out_sxt(s, ext, 0, args[0], args[1]); + break; + case INDEX_op_ext16s_i64: + ext = 1; /* fall through */ + case INDEX_op_ext16s_i32: + tcg_out_sxt(s, ext, 1, args[0], args[1]); + break; + case INDEX_op_ext32s_i64: + tcg_out_sxt(s, 1, 2, args[0], args[1]); + break; + case INDEX_op_ext8u_i64: + case INDEX_op_ext8u_i32: + tcg_out_uxt(s, 0, args[0], args[1]); + break; + case INDEX_op_ext16u_i64: + case INDEX_op_ext16u_i32: + tcg_out_uxt(s, 1, args[0], args[1]); + break; + case INDEX_op_ext32u_i64: + tcg_out_movr(s, 0, args[0], args[1]); + break; + default: tcg_abort(); /* opcode not implemented */ } @@ -1125,6 +1167,18 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_bswap32_i64, { "r", "r" } }, { INDEX_op_bswap64_i64, { "r", "r" } }, + { INDEX_op_ext8s_i32, { "r", "r" } }, + { INDEX_op_ext16s_i32, { "r", "r" } }, + { INDEX_op_ext8u_i32, { "r", "r" } }, + { INDEX_op_ext16u_i32, { "r", "r" } }, + + { INDEX_op_ext8s_i64, { "r", "r" } }, + { INDEX_op_ext16s_i64, { "r", "r" } }, + { INDEX_op_ext32s_i64, { "r", "r" } }, + { INDEX_op_ext8u_i64, { "r", "r" } }, + { INDEX_op_ext16u_i64, { "r", "r" } }, + { INDEX_op_ext32u_i64, { "r", "r" } }, + { -1 }, }; diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 247ef43..97e4a5b 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -40,10 +40,10 @@ typedef enum { /* optional instructions */ #define TCG_TARGET_HAS_div_i32 0 -#define TCG_TARGET_HAS_ext8s_i32 0 -#define TCG_TARGET_HAS_ext16s_i32 0 -#define TCG_TARGET_HAS_ext8u_i32 0 -#define TCG_TARGET_HAS_ext16u_i32 0 +#define TCG_TARGET_HAS_ext8s_i32 1 +#define TCG_TARGET_HAS_ext16s_i32 1 +#define TCG_TARGET_HAS_ext8u_i32 1 +#define TCG_TARGET_HAS_ext16u_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 0 @@ -62,12 +62,12 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_div_i64 0 -#define TCG_TARGET_HAS_ext8s_i64 0 -#define TCG_TARGET_HAS_ext16s_i64 0 -#define TCG_TARGET_HAS_ext32s_i64 0 -#define TCG_TARGET_HAS_ext8u_i64 0 -#define TCG_TARGET_HAS_ext16u_i64 0 -#define TCG_TARGET_HAS_ext32u_i64 0 +#define TCG_TARGET_HAS_ext8s_i64 1 +#define TCG_TARGET_HAS_ext16s_i64 1 +#define TCG_TARGET_HAS_ext32s_i64 1 +#define TCG_TARGET_HAS_ext8u_i64 1 +#define TCG_TARGET_HAS_ext16u_i64 1 +#define TCG_TARGET_HAS_ext32u_i64 1 #define TCG_TARGET_HAS_bswap16_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1