From patchwork Wed Jun 12 15:57:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 250833 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 47DF82C00A0 for ; Thu, 13 Jun 2013 02:29:27 +1000 (EST) Received: from localhost ([::1]:57044 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UmnvJ-0001Rr-DH for incoming@patchwork.ozlabs.org; Wed, 12 Jun 2013 12:29:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Umnr7-0004Sl-DZ for qemu-devel@nongnu.org; Wed, 12 Jun 2013 12:25:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Umnqx-0008On-Pr for qemu-devel@nongnu.org; Wed, 12 Jun 2013 12:25:05 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:57923 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Umnqx-0008OL-Fx for qemu-devel@nongnu.org; Wed, 12 Jun 2013 12:24:55 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1UmnQM-0002MF-KP; Wed, 12 Jun 2013 16:57:26 +0100 From: Peter Maydell To: Aurelien Jarno , Blue Swirl Date: Wed, 12 Jun 2013 16:57:20 +0100 Message-Id: <1371052645-9006-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1371052645-9006-1-git-send-email-peter.maydell@linaro.org> References: <1371052645-9006-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Anthony Liguori , Riku Voipio , Claudio Fontana , qemu-devel@nongnu.org Subject: [Qemu-devel] [PULL 08/13] tcg/aarch64: implement byte swap operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Claudio Fontana implement the optional byte swap operations with the dedicated aarch64 instructions. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Message-id: 51AC9A33.9050003@huawei.com Signed-off-by: Peter Maydell --- tcg/aarch64/tcg-target.c | 32 ++++++++++++++++++++++++++++++++ tcg/aarch64/tcg-target.h | 10 +++++----- 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index bb59794..ba65a62 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -660,6 +660,20 @@ static inline void tcg_out_goto_label_cond(TCGContext *s, } } +static inline void tcg_out_rev(TCGContext *s, int ext, TCGReg rd, TCGReg rm) +{ + /* using REV 0x5ac00800 */ + unsigned int base = ext ? 0xdac00c00 : 0x5ac00800; + tcg_out32(s, base | rm << 5 | rd); +} + +static inline void tcg_out_rev16(TCGContext *s, int ext, TCGReg rd, TCGReg rm) +{ + /* using REV16 0x5ac00400 */ + unsigned int base = ext ? 0xdac00400 : 0x5ac00400; + tcg_out32(s, base | rm << 5 | rd); +} + #ifdef CONFIG_SOFTMMU #include "exec/softmmu_defs.h" @@ -1012,6 +1026,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, 3); break; + case INDEX_op_bswap64_i64: + ext = 1; /* fall through */ + case INDEX_op_bswap32_i64: + case INDEX_op_bswap32_i32: + tcg_out_rev(s, ext, args[0], args[1]); + break; + case INDEX_op_bswap16_i64: + case INDEX_op_bswap16_i32: + tcg_out_rev16(s, 0, args[0], args[1]); + break; + default: tcg_abort(); /* opcode not implemented */ } @@ -1093,6 +1118,13 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_qemu_st16, { "l", "l" } }, { INDEX_op_qemu_st32, { "l", "l" } }, { INDEX_op_qemu_st64, { "l", "l" } }, + + { INDEX_op_bswap16_i32, { "r", "r" } }, + { INDEX_op_bswap32_i32, { "r", "r" } }, + { INDEX_op_bswap16_i64, { "r", "r" } }, + { INDEX_op_bswap32_i64, { "r", "r" } }, + { INDEX_op_bswap64_i64, { "r", "r" } }, + { -1 }, }; diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 075ab2a..247ef43 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -44,8 +44,8 @@ typedef enum { #define TCG_TARGET_HAS_ext16s_i32 0 #define TCG_TARGET_HAS_ext8u_i32 0 #define TCG_TARGET_HAS_ext16u_i32 0 -#define TCG_TARGET_HAS_bswap16_i32 0 -#define TCG_TARGET_HAS_bswap32_i32 0 +#define TCG_TARGET_HAS_bswap16_i32 1 +#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 0 #define TCG_TARGET_HAS_neg_i32 0 #define TCG_TARGET_HAS_rot_i32 1 @@ -68,9 +68,9 @@ typedef enum { #define TCG_TARGET_HAS_ext8u_i64 0 #define TCG_TARGET_HAS_ext16u_i64 0 #define TCG_TARGET_HAS_ext32u_i64 0 -#define TCG_TARGET_HAS_bswap16_i64 0 -#define TCG_TARGET_HAS_bswap32_i64 0 -#define TCG_TARGET_HAS_bswap64_i64 0 +#define TCG_TARGET_HAS_bswap16_i64 1 +#define TCG_TARGET_HAS_bswap32_i64 1 +#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_not_i64 0 #define TCG_TARGET_HAS_neg_i64 0 #define TCG_TARGET_HAS_rot_i64 1