Patchwork [v2,2/5] intc/xilinx_intc: Don't clear level sens. IRQs without ACK

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Submitter Peter Crosthwaite
Date June 11, 2013, 12:58 a.m.
Message ID <9fac9e29fe1807f22bf51daef9978d91c2872d42.1370911981.git.peter.crosthwaite@xilinx.com>
Download mbox | patch
Permalink /patch/250429/
State New
Headers show

Comments

Peter Crosthwaite - June 11, 2013, 12:58 a.m.
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

For level sensitive interrupts, ISR bits are cleared when the input pin
is lowered. This is incorrect. Only software can clear ISR bits (via
IAR or direct write to ISR with !MER(2)).

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 hw/intc/xilinx_intc.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

Patch

diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index b106e72..a585ba1 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -139,13 +139,7 @@  static void irq_handler(void *opaque, int irq, int level)
         return;
     }
 
-    /* Update source flops. Don't clear unless level triggered.
-       Edge triggered interrupts only go away when explicitely acked to
-       the interrupt controller.  */
-    if (!(p->c_kind_of_intr & (1 << irq)) || level) {
-        p->regs[R_ISR] &= ~(1 << irq);
-        p->regs[R_ISR] |= (level << irq);
-    }
+    p->regs[R_ISR] |= (level << irq);
     update_irq(p);
 }