| Message ID | CAKdSQZk1ZKhrFAsqMxxsFSEdsPT7ocu3Mahwd+OLkRWVAQ_NUw@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
On Mon, Jun 10, 2013 at 3:25 PM, Igor Zamyatin <izamyatin@gmail.com> wrote: > Following patch documents Intel Silvermont support. > > OK to install? > > Thanks, > Igor > > > Changelog: > > > 2013-06-10 Igor Zamyatin <igor.zamyatin@intel.com> > > * doc/invoke.texi: Document slm. > > > > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index b7b32f7..e4f1d45 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -13837,6 +13837,10 @@ set support. > Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 > instruction set support. > > +@item slm > +Intel Silvermont CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3, > +SSE4.1, SSE4.2 instruction set support. SSE4.1 and SSE4.2 instruction set support. OK with this change. Thanks, Uros.
On Mon, Jun 10, 2013 at 05:25:36PM +0400, Igor Zamyatin wrote: > Following patch documents Intel Silvermont support. > > OK to install? > > 2013-06-10 Igor Zamyatin <igor.zamyatin@intel.com> > > * doc/invoke.texi: Document slm. > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index b7b32f7..e4f1d45 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -13837,6 +13837,10 @@ set support. > Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 > instruction set support. > > +@item slm > +Intel Silvermont CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3, > +SSE4.1, SSE4.2 instruction set support. Shouldn't it also list MOVBE (similarly for atom and core-avx2, btver2 already lists it). core-avx2 isn't even documented at all in invoke.texi. Jakub
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b7b32f7..e4f1d45 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13837,6 +13837,10 @@ set support. Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. +@item slm +Intel Silvermont CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3, +SSE4.1, SSE4.2 instruction set support. + @item k6 AMD K6 CPU with MMX instruction set support.
Hi! Following patch documents Intel Silvermont support. OK to install? Thanks, Igor Changelog: 2013-06-10 Igor Zamyatin <igor.zamyatin@intel.com> * doc/invoke.texi: Document slm.