From patchwork Sun Jun 9 02:53:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keguang Zhang X-Patchwork-Id: 250003 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ozlabs.org (Postfix) with ESMTP id C6A742C0097 for ; Sun, 9 Jun 2013 12:54:07 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 93A95894FC; Sun, 9 Jun 2013 02:54:04 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HrwEP3k-kGrB; Sun, 9 Jun 2013 02:54:03 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by whitealder.osuosl.org (Postfix) with ESMTP id 239B48975F; Sun, 9 Jun 2013 02:54:03 +0000 (UTC) X-Original-To: buildroot@lists.busybox.net Delivered-To: buildroot@osuosl.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id B268C8F7B0 for ; Sun, 9 Jun 2013 02:54:08 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 8A5A7894FC for ; Sun, 9 Jun 2013 02:54:01 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ortH44EeXnzZ for ; Sun, 9 Jun 2013 02:54:00 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mail-pd0-f174.google.com (mail-pd0-f174.google.com [209.85.192.174]) by whitealder.osuosl.org (Postfix) with ESMTPS id 58B8284E92 for ; Sun, 9 Jun 2013 02:54:00 +0000 (UTC) Received: by mail-pd0-f174.google.com with SMTP id 10so5196416pdc.5 for ; Sat, 08 Jun 2013 19:54:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=7NLVOAYT7H4HH7VuSXqk6JXlRg5TdQ6jVR7e/X4HKVw=; b=VM+7rUsmFKWCp9NnitW+KMNlL1bAUYGYi2dj+i3jFBd0sJReM4gB+OS9A9Plt+vOqr rVPSIkmZS0yKLIabzznioB9Z1mA+/3cNv7RgOS2kUd7LStcpZQMlvOWVtAGxHu9DLyJ3 Ux2IsoJT0V94YzbSUT5TZoje/UvoMx234yXUAOuDyxN3615yC6D9dmNuV5ZRbqObvDOS /d+xFKVbM53e7eNWztofaqFbhtQunR6EQhgYwAcx+QJMMkuPiQOpt9lLNPVkdlolOQYw vFjljsCY5jGg7SnRDgQO0f1ml98Dp5p56q7w32qAkNFIBvg+4fiVvqnrFXjPY8zp6pNq zPsg== X-Received: by 10.66.245.110 with SMTP id xn14mr8728156pac.130.1370746440147; Sat, 08 Jun 2013 19:54:00 -0700 (PDT) Received: from localhost.localdomain ([110.191.40.90]) by mx.google.com with ESMTPSA id ih1sm4873737pbb.44.2013.06.08.19.53.55 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 08 Jun 2013 19:53:59 -0700 (PDT) From: Kelvin Cheung To: buildroot@busybox.net Date: Sun, 9 Jun 2013 10:53:50 +0800 Message-Id: <1370746430-5135-1-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.9.5 Subject: [Buildroot] [PATCH] arm: update processor types X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.14 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: buildroot-bounces@busybox.net Update arm architecture variant: add the cortex A7. Signed-off-by: Kelvin Cheung --- arch/Config.in.arm | 5 +++++ toolchain/gcc/Config.in | 8 ++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/Config.in.arm b/arch/Config.in.arm index 2f4c0c8..983cac4 100644 --- a/arch/Config.in.arm +++ b/arch/Config.in.arm @@ -36,6 +36,9 @@ config BR2_arm1176jzf_s config BR2_cortex_a5 bool "cortex-A5" select BR2_ARM_CPU_MAYBE_HAS_NEON +config BR2_cortex_a7 + bool "cortex-A7" + select BR2_ARM_CPU_HAS_NEON config BR2_cortex_a8 bool "cortex-A8" select BR2_ARM_CPU_HAS_NEON @@ -113,6 +116,7 @@ config BR2_GCC_TARGET_TUNE default "arm1176jz-s" if BR2_arm1176jz_s default "arm1176jzf-s" if BR2_arm1176jzf_s default "cortex-a5" if BR2_cortex_a5 + default "cortex-a7" if BR2_cortex_a7 default "cortex-a8" if BR2_cortex_a8 default "cortex-a9" if BR2_cortex_a9 default "cortex-a15" if BR2_cortex_a15 @@ -134,6 +138,7 @@ config BR2_GCC_TARGET_ARCH default "armv6zk" if BR2_arm1176jz_s default "armv6zk" if BR2_arm1176jzf_s default "armv7-a" if BR2_cortex_a5 + default "armv7-a" if BR2_cortex_a7 default "armv7-a" if BR2_cortex_a8 default "armv7-a" if BR2_cortex_a9 default "armv7-a" if BR2_cortex_a15 diff --git a/toolchain/gcc/Config.in b/toolchain/gcc/Config.in index fdb19e1..7830241 100644 --- a/toolchain/gcc/Config.in +++ b/toolchain/gcc/Config.in @@ -23,20 +23,20 @@ choice bool "gcc 4.2.2-avr32-2.1.5" config BR2_GCC_VERSION_4_3_X - depends on !BR2_arc && !BR2_avr32 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_cortex_a5 && !BR2_cortex_a8 && !BR2_cortex_a9 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_powerpc_e300c2 && !BR2_powerpc_e300c3 && !BR2_powerpc_e500mc && !BR2_powerpc_464 && !BR2_powerpc_464fp && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 + depends on !BR2_arc && !BR2_avr32 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_cortex_a5 && !BR2_cortex_a7 && !BR2_cortex_a8 && !BR2_cortex_a9 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_powerpc_e300c2 && !BR2_powerpc_e300c3 && !BR2_powerpc_e500mc && !BR2_powerpc_464 && !BR2_powerpc_464fp && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 bool "gcc 4.3.x" config BR2_GCC_VERSION_4_4_X - depends on !BR2_arc && !BR2_avr32 && !BR2_cortex_a5 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 + depends on !BR2_arc && !BR2_avr32 && !BR2_cortex_a5 && !BR2_cortex_a7 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 bool "gcc 4.4.x" config BR2_GCC_VERSION_4_5_X - depends on !BR2_arc && !BR2_avr32 && !BR2_cortex_a15 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_fa526 && !BR2_pj4 + depends on !BR2_arc && !BR2_avr32 && !BR2_cortex_a7 && !BR2_cortex_a15 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_fa526 && !BR2_pj4 select BR2_GCC_NEEDS_MPC bool "gcc 4.5.x" config BR2_GCC_VERSION_4_6_X - depends on !BR2_arc && !BR2_avr32 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_pj4 + depends on !BR2_arc && !BR2_avr32 && !BR2_cortex_a7 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_pj4 select BR2_GCC_NEEDS_MPC bool "gcc 4.6.x"