From patchwork Sat Jun 8 17:44:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Herv=C3=A9_Poussineau?= X-Patchwork-Id: 249973 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 913252C0096 for ; Sun, 9 Jun 2013 03:46:24 +1000 (EST) Received: from localhost ([::1]:46635 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UlNDa-0005Y0-N8 for incoming@patchwork.ozlabs.org; Sat, 08 Jun 2013 13:46:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UlNB3-0001RR-Df for qemu-devel@nongnu.org; Sat, 08 Jun 2013 13:43:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UlNB2-0006UP-71 for qemu-devel@nongnu.org; Sat, 08 Jun 2013 13:43:45 -0400 Received: from [101.78.175.194] (port=46178 helo=ibis.ibis) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UlNB1-0006UK-On for qemu-devel@nongnu.org; Sat, 08 Jun 2013 13:43:44 -0400 Received: from [172.19.126.47] (helo=localhost.localdomain) by ibis.ibis with esmtp (Exim 4.70) (envelope-from ) id 1UlNAy-0000wp-T5; Sun, 09 Jun 2013 01:43:41 +0800 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= To: qemu-devel@nongnu.org Date: Sun, 9 Jun 2013 01:44:05 +0800 Message-Id: <1370713446-9460-8-git-send-email-hpoussin@reactos.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1370713446-9460-1-git-send-email-hpoussin@reactos.org> References: <1370713446-9460-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 101.78.175.194 Cc: Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , qemu-ppc@nongnu.org, Alexander Graf , David Gibson Subject: [Qemu-devel] [PATCH v2 7/8] PPC: pseries: Remove hack for PIO window X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Alexander Graf Now that all users of old_portio are gone, we can remove the hack that enabled us to support them. This is the same commit as a178274efabcbbc5d44805b51def874e47051325, which has been reverted in a3cfa18eb075c7ef78358ca1956fe7b01caa1724. Signed-off-by: Hervé Poussineau --- hw/ppc/spapr_pci.c | 44 +------------------------------------------ include/hw/pci-host/spapr.h | 2 +- 2 files changed, 2 insertions(+), 44 deletions(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 62ff323..161d570 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -439,43 +439,6 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); } -static uint64_t spapr_io_read(void *opaque, hwaddr addr, - unsigned size) -{ - switch (size) { - case 1: - return cpu_inb(addr); - case 2: - return cpu_inw(addr); - case 4: - return cpu_inl(addr); - } - assert(0); -} - -static void spapr_io_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) -{ - switch (size) { - case 1: - cpu_outb(addr, data); - return; - case 2: - cpu_outw(addr, data); - return; - case 4: - cpu_outl(addr, data); - return; - } - assert(0); -} - -static const MemoryRegionOps spapr_io_ops = { - .endianness = DEVICE_LITTLE_ENDIAN, - .read = spapr_io_read, - .write = spapr_io_write -}; - /* * MSI/MSIX memory region implementation. * The handler handles both MSI and MSIX. @@ -599,14 +562,9 @@ static int spapr_phb_init(SysBusDevice *s) * old_portion are updated */ sprintf(namebuf, "%s.io", sphb->dtbusname); memory_region_init(&sphb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE); - /* FIXME: fix to support multiple PHBs */ - memory_region_add_subregion(get_system_io(), 0, &sphb->iospace); - sprintf(namebuf, "%s.io-alias", sphb->dtbusname); - memory_region_init_io(&sphb->iowindow, &spapr_io_ops, sphb, - namebuf, SPAPR_PCI_IO_WIN_SIZE); memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, - &sphb->iowindow); + &sphb->iospace); /* As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, * we need to allocate some memory to catch those writes coming diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index b21080c..dabef16 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -44,7 +44,7 @@ typedef struct sPAPRPHBState { MemoryRegion memspace, iospace; hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size; hwaddr msi_win_addr; - MemoryRegion memwindow, iowindow, msiwindow; + MemoryRegion memwindow, msiwindow; uint32_t dma_liobn; uint64_t dma_window_start;