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[114.44.53.234]) by mx.google.com with ESMTPSA id xn5sm5120242pab.0.2013.06.07.20.14.42 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 07 Jun 2013 20:14:44 -0700 (PDT) From: Kuan-Yu Kuo To: u-boot@lists.denx.de, wd@denx.de, dzu@denx.de Date: Sat, 8 Jun 2013 11:14:09 +0800 Message-Id: <1370661252-12156-1-git-send-email-ken.kuoky@gmail.com> X-Mailer: git-send-email 1.7.9 Cc: uboot@andestech.com Subject: [U-Boot] [PATCH 1/4] nds32: Enable two banks of SDRAM on Andes board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The original adp-ag101/adp-ag101p initialize only one bank(64MB) by default at boot time, but it is not enough for some application, so increasing to two banks(128M). Signed-off-by: Kuan-Yu Kuo Cc: Macpaul Lin --- arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 6 +++++- board/AndesTech/adp-ag101/adp-ag101.c | 10 +++++++++- board/AndesTech/adp-ag101p/adp-ag101p.c | 10 +++++++++- include/configs/adp-ag101.h | 10 +++++++++- include/configs/adp-ag101p.h | 9 ++++++++- 5 files changed, 40 insertions(+), 5 deletions(-) diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S index 29c93fe..55985cf 100644 --- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S @@ -38,6 +38,7 @@ #define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1) #define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2) #define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR) +#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR) #define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1 #define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2 @@ -45,6 +46,7 @@ #define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2 #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR +#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR /* * parameters for the static memory controller @@ -167,12 +169,12 @@ relo_base: */ led 0x1a write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001100 + write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001140 /* clear empty BSR registers */ led 0x1b li $r4, CONFIG_FTSDMC021_BASE li $r5, 0x0 - swi $r5, [$r4 + FTSDMC021_BANK1_BSR] swi $r5, [$r4 + FTSDMC021_BANK2_BSR] swi $r5, [$r4 + FTSDMC021_BANK3_BSR] @@ -223,6 +225,8 @@ relo_base: * - after remap: flash/rom 0x80000000, sdram: 0x00000000 */ led 0x1c + write32 SDMC_B0_BSR_A, 0x00001000 + write32 SDMC_B1_BSR_A, 0x00001040 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1 #endif /* #ifdef CONFIG_MEM_REMAP */ diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c index 82ce4c9..ebc20a5 100644 --- a/board/AndesTech/adp-ag101/adp-ag101.c +++ b/board/AndesTech/adp-ag101/adp-ag101.c @@ -50,7 +50,7 @@ int board_init(void) int dram_init(void) { unsigned long sdram_base = PHYS_SDRAM_0; - unsigned long expected_size = PHYS_SDRAM_0_SIZE; + unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; unsigned long actual_size; actual_size = get_ram_size((void *)sdram_base, expected_size); @@ -65,6 +65,14 @@ int dram_init(void) return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_0; + gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE; +} + int board_eth_init(bd_t *bd) { return ftmac100_initialize(bd); diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c index 8dd2043..26d67e2 100644 --- a/board/AndesTech/adp-ag101p/adp-ag101p.c +++ b/board/AndesTech/adp-ag101p/adp-ag101p.c @@ -50,7 +50,7 @@ int board_init(void) int dram_init(void) { unsigned long sdram_base = PHYS_SDRAM_0; - unsigned long expected_size = PHYS_SDRAM_0_SIZE; + unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; unsigned long actual_size; actual_size = get_ram_size((void *)sdram_base, expected_size); @@ -65,6 +65,14 @@ int dram_init(void) return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_0; + gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE; +} + int board_eth_init(bd_t *bd) { return ftmac100_initialize(bd); diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h index b6e3844..1b84b04 100644 --- a/include/configs/adp-ag101.h +++ b/include/configs/adp-ag101.h @@ -235,6 +235,11 @@ #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ CONFIG_SYS_FTSDMC021_BANK0_BASE) +#define CONFIG_SYS_FTSDMC021_BANK1_BASE \ + (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) +#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ + CONFIG_SYS_FTSDMC021_BANK1_BASE) + #endif /* @@ -248,9 +253,12 @@ #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ #endif +#define PHYS_SDRAM_1 \ + (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index ef55e35..cec89f6 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -236,6 +236,10 @@ #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ CONFIG_SYS_FTSDMC021_BANK0_BASE) +#define CONFIG_SYS_FTSDMC021_BANK1_BASE \ + (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) +#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ + CONFIG_SYS_FTSDMC021_BANK1_BASE) #endif /* @@ -249,9 +253,12 @@ #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ #endif +#define PHYS_SDRAM_1 \ + (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0