From patchwork Fri Jun 7 16:50:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cesar Philippidis X-Patchwork-Id: 249760 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 1CFFD2C0304 for ; Sat, 8 Jun 2013 02:50:44 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=Xc8DqjsMjxXQYRIun eL+KJ/h1TCgGsFdnIkSh5KhrjC4ndKRWl53/PuAmOVGMQ6V4ZKhUUQMj433JR0E6 DiUEe1OezQayqBMfhKJxG2WIjmSq5oCRmcI46bamAhHH7yDlk6NCqOBicWmOYdiX OkiDhQUQY0gFi2ucnhyEh8xpUg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=A3tsnvIZDC4V6JOCNDcidFH QS68=; b=WAESPt2hANt5anZV8GMiHJjlhmq50Wve/+hhxlm9AibAsEqCVkC/uuV V5AIezNyIY5fitZ2ZKLMXx5xDQbwcP/3uyvUvLq6kdZPzx5QZgLSq11aMhss/25C 2UsUxVdaiJjsjZe1ybmwd5xeqw01nii8fAkE1k7FLeW3eNZXzlPo= Received: (qmail 20532 invoked by alias); 7 Jun 2013 16:50:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 20522 invoked by uid 89); 7 Jun 2013 16:50:37 -0000 X-Spam-SWARE-Status: No, score=-4.2 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, KHOP_THREADED, RCVD_IN_HOSTKARMA_W, RCVD_IN_HOSTKARMA_WL autolearn=ham version=3.3.1 Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Fri, 07 Jun 2013 16:50:36 +0000 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1Ukzs2-0000Iv-BV from Cesar_Philippidis@mentor.com ; Fri, 07 Jun 2013 09:50:34 -0700 Received: from SVR-ORW-FEM-04.mgc.mentorg.com ([147.34.97.41]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 7 Jun 2013 09:50:33 -0700 Received: from mbp17.localdomain (147.34.91.1) by svr-orw-fem-04.mgc.mentorg.com (147.34.97.41) with Microsoft SMTP Server id 14.2.247.3; Fri, 7 Jun 2013 09:50:33 -0700 Message-ID: <51B20F5A.5000908@codesourcery.com> Date: Fri, 7 Jun 2013 09:50:34 -0700 From: Cesar Philippidis User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.8; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 MIME-Version: 1.0 To: Richard Earnshaw CC: "gcc-patches@gcc.gnu.org" , Ramana Radhakrishnan , Julian Brown Subject: Re: [PATCH] ARMv6-M MI thunk fix References: <51B0AE22.2070209@codesourcery.com> <51B0B233.7070701@arm.com> In-Reply-To: <51B0B233.7070701@arm.com> X-Virus-Found: No On 6/6/13 9:00 AM, Richard Earnshaw wrote: > The pipeline offset is 4 for Thumb2 as well. So at the very least you > need to explain why your change doesn't apply then as well. Yes some context is lost in that comment. Thunks are usually emitted in ARM mode, except for Thumb-only targets. Is the new comment OK? If so, please check it in since I do not have SVN write access. Thanks, Cesar 2013-06-07 Julian Brown Cesar Philippidis gcc/ * config/arm/arm.c (arm_output_mi_thunk): Fix offset for TARGET_THUMB1_ONLY. Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 199695) +++ gcc/config/arm/arm.c (working copy) @@ -25217,7 +25217,12 @@ { /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */ rtx tem = XEXP (DECL_RTL (function), 0); - tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7)); + /* When supported, thunks are generated in ARM mode. But for + TARGET_THUMB1_ONLY the thunk is in Thumb mode, so the PC + pipeline offset is four rather than eight. Adjust the + offset accordingly. */ + tem = gen_rtx_PLUS (GET_MODE (tem), tem, + GEN_INT (TARGET_THUMB1_ONLY ? -3 : -7)); tem = gen_rtx_MINUS (GET_MODE (tem), tem, gen_rtx_SYMBOL_REF (Pmode,