[v1,2/5] intc/xilinx_intc: Don't clear level sens. IRQs without ACK

Submitted by Peter Crosthwaite on June 7, 2013, 2:38 a.m.

Details

Message ID 734e40a42d5544050b984019303402432f9e6be5.1370572420.git.peter.crosthwaite@xilinx.com
State New
Headers show

Commit Message

Peter Crosthwaite June 7, 2013, 2:38 a.m.
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

For level sensitive interrupts, ISR bits are cleared when the input pin
is lowered. This is incorrect. Only software can clear ISR bits (via
IAR or direct write to ISR with !MER(2)).

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 hw/intc/xilinx_intc.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

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diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 5df7008..d243a00 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -135,13 +135,7 @@  static void irq_handler(void *opaque, int irq, int level)
         return;
     }
 
-    /* Update source flops. Don't clear unless level triggered.
-       Edge triggered interrupts only go away when explicitely acked to
-       the interrupt controller.  */
-    if (!(p->c_kind_of_intr & (1 << irq)) || level) {
-        p->regs[R_ISR] &= ~(1 << irq);
-        p->regs[R_ISR] |= (level << irq);
-    }
+    p->regs[R_ISR] |= (level << irq);
     update_irq(p);
 }