From patchwork Wed Jun 5 20:22:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lijun Pan X-Patchwork-Id: 249186 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id BAF9D2C071A for ; Thu, 6 Jun 2013 06:24:38 +1000 (EST) Received: by ozlabs.org (Postfix) id E08B82C030A; Thu, 6 Jun 2013 06:22:20 +1000 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from db8outboundpool.messaging.microsoft.com (mail-db8lp0187.outbound.messaging.microsoft.com [213.199.154.187]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "MSIT Machine Auth CA 2" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 4EF1B2C02F4 for ; Thu, 6 Jun 2013 06:22:20 +1000 (EST) Received: from mail165-db8-R.bigfish.com (10.174.8.251) by DB8EHSOBE007.bigfish.com (10.174.4.70) with Microsoft SMTP Server id 14.1.225.23; Wed, 5 Jun 2013 20:22:16 +0000 Received: from mail165-db8 (localhost [127.0.0.1]) by mail165-db8-R.bigfish.com (Postfix) with ESMTP id BE8F6AC00E7 for ; Wed, 5 Jun 2013 20:22:16 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ah1fc6hzz8275bhz2dh2a8h668h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e23h1155h) Received: from mail165-db8 (localhost.localdomain [127.0.0.1]) by mail165-db8 (MessageSwitch) id 1370463734564996_15056; Wed, 5 Jun 2013 20:22:14 +0000 (UTC) Received: from DB8EHSMHS006.bigfish.com (unknown [10.174.8.229]) by mail165-db8.bigfish.com (Postfix) with ESMTP id 878668E0045 for ; Wed, 5 Jun 2013 20:22:14 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS006.bigfish.com (10.174.4.16) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 5 Jun 2013 20:22:13 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.328.11; Wed, 5 Jun 2013 20:23:26 +0000 Received: from right.am.freescale.net (right.am.freescale.net [10.82.176.228]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r55KMA2h017373; Wed, 5 Jun 2013 13:22:10 -0700 From: Lijun Pan To: Subject: [PATCH 2/4] powerpc/perf: increase the perf HW events to 6 Date: Wed, 5 Jun 2013 15:22:08 -0500 Message-ID: <1370463730-23733-2-git-send-email-Lijun.Pan@freescale.com> X-Mailer: git-send-email 1.7.9.7 In-Reply-To: <1370463730-23733-1-git-send-email-Lijun.Pan@freescale.com> References: <1370463730-23733-1-git-send-email-Lijun.Pan@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Lijun.Pan@freescale.com, Catalin Udma X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Catalin Udma This change is required after the e6500 perf support has been added. There are 6 counters in e6500 core instead of 4 in e500 core and the MAX_HWEVENTS counter should be changed accordingly from 4 to 6. Added also runtime check for counters overflow. Signed-off-by: Catalin Udma Signed-off-by: Lijun Pan --- arch/powerpc/include/asm/perf_event_fsl_emb.h | 2 +- arch/powerpc/perf/core-fsl-emb.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/perf_event_fsl_emb.h b/arch/powerpc/include/asm/perf_event_fsl_emb.h index 718a9fa..a581654 100644 --- a/arch/powerpc/include/asm/perf_event_fsl_emb.h +++ b/arch/powerpc/include/asm/perf_event_fsl_emb.h @@ -13,7 +13,7 @@ #include #include -#define MAX_HWEVENTS 4 +#define MAX_HWEVENTS 6 /* event flags */ #define FSL_EMB_EVENT_VALID 1 diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c index 106c533..0b13f74 100644 --- a/arch/powerpc/perf/core-fsl-emb.c +++ b/arch/powerpc/perf/core-fsl-emb.c @@ -462,6 +462,12 @@ static int fsl_emb_pmu_event_init(struct perf_event *event) int num_restricted; int i; + if (ppmu->n_counter > MAX_HWEVENTS) { + WARN(1, "No. of perf counters (%d) is higher than max array size(%d)\n", + ppmu->n_counter, MAX_HWEVENTS); + ppmu->n_counter = MAX_HWEVENTS; + } + switch (event->attr.type) { case PERF_TYPE_HARDWARE: ev = event->attr.config;