From patchwork Mon Jun 3 16:34:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Bolton X-Patchwork-Id: 248342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 364B82C0099 for ; Tue, 4 Jun 2013 02:35:07 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=QTWzONOrLFsOjfMuRkaYCu/F+13u5+HTlB4Hq5X7cfWvE3VVo5Obv QjZ333wr1+9M5RfEk/D5LfhdxjrmGzzMIERmkfY8oqC/usqfEFpwVWXb0x02c+vF Jgyy5ik5HCiiEjVwLcfF2mW4JWR7yupiVqv+mAcZ21Jt3VzQehE/PA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=AFvuIvGR864WItd7+Z/VhKWJvXY=; b=Igb+KPHFuyxgpEkpZp6k j8ric1r4k2cj9a3SM4cURXG4h4IO78c34lhe4fKO1b23pPk/JvrQrqCyb+07YoDO gJNfoHnKssSDYv+0SredxLKUiWt01GvpBIgx6aJhtWuk9A73e1CpaaqLkcEamojU 4/EBTYXIkdSjYYLEDW7Fsek= Received: (qmail 25084 invoked by alias); 3 Jun 2013 16:35:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25055 invoked by uid 89); 3 Jun 2013 16:35:00 -0000 X-Spam-SWARE-Status: No, score=-0.2 required=5.0 tests=AWL, BAYES_50, MSGID_MULTIPLE_AT, RCVD_IN_DNSWL_LOW, SPF_PASS, TW_MV, TW_NV, TW_XF autolearn=no version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Mon, 03 Jun 2013 16:34:59 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 03 Jun 2013 17:34:56 +0100 Received: from E102352xp ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 Jun 2013 17:34:55 +0100 From: "Ian Bolton" To: Subject: [AArch64, PATCH 4/5] Improve MOVI handling (Other minor clean-up) Date: Mon, 3 Jun 2013 17:34:52 +0100 Message-ID: <000c01ce6078$45d1ea50$d175bef0$@bolton@arm.com> MIME-Version: 1.0 X-MC-Unique: 113060317345606501 X-Virus-Found: No (This patch is the fourth of five, where the first 4 do some clean-up and the last fixes a bug with scalar MOVI. The bug fix without the clean-up was particularly ugly!) I think the changelog says it all here. Nothing major, just tidying up. OK for trunk? Cheers, Ian 2013-06-03 Ian Bolton * config/aarch64/aarch64.c (simd_immediate_info): Remove element_char member. (sizetochar): Return signed char. (aarch64_simd_valid_immediate): Remove elchar and other unnecessary variables. (aarch64_output_simd_mov_immediate): Take rtx instead of &rtx. Calculate element_char as required. * config/aarch64/aarch64-protos.h: Update and move prototype for aarch64_output_simd_mov_immediate. * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): Update arguments. diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 083ce91..d21a2f5 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -148,6 +148,7 @@ bool aarch64_legitimate_pic_operand_p (rtx); bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode); bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context, enum machine_mode); +char *aarch64_output_simd_mov_immediate (rtx, enum machine_mode, unsigned); bool aarch64_pad_arg_upward (enum machine_mode, const_tree); bool aarch64_pad_reg_upward (enum machine_mode, const_tree, bool); bool aarch64_regno_ok_for_base_p (int, bool); @@ -258,6 +259,4 @@ extern void aarch64_split_combinev16qi (rtx operands[3]); extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); extern bool aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); - -char* aarch64_output_simd_mov_immediate (rtx *, enum machine_mode, unsigned); #endif /* GCC_AARCH64_PROTOS_H */ diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 04fbdbd..e5990d4 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -409,7 +409,7 @@ case 4: return "ins\t%0.d[0], %1"; case 5: return "mov\t%0, %1"; case 6: - return aarch64_output_simd_mov_immediate (&operands[1], + return aarch64_output_simd_mov_immediate (operands[1], mode, 64); default: gcc_unreachable (); } @@ -440,7 +440,7 @@ case 5: return "#"; case 6: - return aarch64_output_simd_mov_immediate (&operands[1], mode, 128); + return aarch64_output_simd_mov_immediate (operands[1], mode, 128); default: gcc_unreachable (); } diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d83e645..001f9c5 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -91,7 +91,6 @@ struct simd_immediate_info { rtx value; int shift; int element_width; - unsigned char element_char; bool mvn; }; @@ -6102,7 +6101,7 @@ aarch64_mangle_type (const_tree type) } /* Return the equivalent letter for size. */ -static unsigned char +static char sizetochar (int size) { switch (size) @@ -6163,7 +6162,6 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, bool inverse, { \ immtype = (CLASS); \ elsize = (ELSIZE); \ - elchar = sizetochar (elsize); \ eshift = (SHIFT); \ emvn = (NEG); \ break; \ @@ -6172,25 +6170,20 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, bool inverse, unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); unsigned char bytes[16]; - unsigned char elchar = 0; int immtype = -1, matches; unsigned int invmask = inverse ? 0xff : 0; int eshift, emvn; if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) { - bool simd_imm_zero = aarch64_simd_imm_zero_p (op, mode); - int elem_width = GET_MODE_BITSIZE (GET_MODE (CONST_VECTOR_ELT (op, 0))); - - if (!(simd_imm_zero - || aarch64_vect_float_const_representable_p (op))) + if (! (aarch64_simd_imm_zero_p (op, mode) + || aarch64_vect_float_const_representable_p (op))) return false; if (info) { info->value = CONST_VECTOR_ELT (op, 0); - info->element_width = elem_width; - info->element_char = sizetochar (elem_width); + info->element_width = GET_MODE_BITSIZE (GET_MODE (info->value)); info->mvn = false; info->shift = 0; } @@ -6298,7 +6291,6 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, bool inverse, if (info) { info->element_width = elsize; - info->element_char = elchar; info->mvn = emvn != 0; info->shift = eshift; @@ -7228,7 +7220,7 @@ aarch64_float_const_representable_p (rtx x) } char* -aarch64_output_simd_mov_immediate (rtx *const_vector, +aarch64_output_simd_mov_immediate (rtx const_vector, enum machine_mode mode, unsigned width) { @@ -7236,16 +7228,17 @@ aarch64_output_simd_mov_immediate (rtx *const_vector, static char templ[40]; const char *mnemonic; unsigned int lane_count = 0; + char element_char; struct simd_immediate_info info; /* This will return true to show const_vector is legal for use as either a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will also update INFO to show how the immediate should be generated. */ - is_valid = aarch64_simd_valid_immediate (*const_vector, mode, false, &info); + is_valid = aarch64_simd_valid_immediate (const_vector, mode, false, &info); gcc_assert (is_valid); - gcc_assert (info.element_width != 0); + element_char = sizetochar (info.element_width); lane_count = width / info.element_width; mode = GET_MODE_INNER (mode); @@ -7267,7 +7260,7 @@ aarch64_output_simd_mov_immediate (rtx *const_vector, snprintf (templ, sizeof (templ), "fmov\t%%d0, %s", float_buf); else snprintf (templ, sizeof (templ), "fmov\t%%0.%d%c, %s", - lane_count, info.element_char, float_buf); + lane_count, element_char, float_buf); return templ; } } @@ -7279,11 +7272,11 @@ aarch64_output_simd_mov_immediate (rtx *const_vector, mnemonic, UINTVAL (info.value)); else if (info.shift) snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, " HOST_WIDE_INT_PRINT_HEX - ", lsl %d", mnemonic, lane_count, info.element_char, + ", lsl %d", mnemonic, lane_count, element_char, UINTVAL (info.value), info.shift); else snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, " HOST_WIDE_INT_PRINT_HEX, - mnemonic, lane_count, info.element_char, UINTVAL (info.value)); + mnemonic, lane_count, element_char, UINTVAL (info.value)); return templ; }