@@ -37,8 +37,10 @@ (define_insn_reservation "ppc403-store" 2
"iu_40x")
(define_insn_reservation "ppc403-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ cntlz,exts,isel")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
@@ -53,8 +55,10 @@ (define_insn_reservation "ppc403-three" 1
"iu_40x,iu_40x,iu_40x")
(define_insn_reservation "ppc403-compare" 3
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
+ var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,nothing,bpu_40x")
@@ -54,8 +54,10 @@ (define_insn_reservation "ppc440-fpstore" 3
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
- trap,var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ trap,cntlz,exts,isel")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
@@ -64,7 +64,9 @@ (define_insn_reservation "ppc476-fpstore" 4
ppc476_lj_pipe")
(define_insn_reservation "ppc476-simple-integer" 1
- (and (eq_attr "type" "integer,insert_word,var_shift_rotate,exts,shift")
+ (and (ior (eq_attr "type" "integer,insert_word,exts,shift")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe|ppc476_lj_pipe")
@@ -76,8 +78,10 @@ (define_insn_reservation "ppc476-complex-integer" 1
ppc476_i_pipe")
(define_insn_reservation "ppc476-compare" 4
- (and (eq_attr "type" "compare,delayed_compare,fast_compare,mfcr,mfcrf,\
- mtcr,mfjmpr,mtjmpr,var_delayed_compare")
+ (and (ior (eq_attr "type" "compare,delayed_compare,fast_compare,mfcr,mfcrf,\
+ mtcr,mfjmpr,mtjmpr,var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
@@ -46,8 +46,10 @@ (define_insn_reservation "ppc601-fpstore" 3
"iu_ppc601+fpu_ppc601")
(define_insn_reservation "ppc601-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
- trap,var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ trap,cntlz,exts,isel")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
@@ -74,8 +76,9 @@ (define_insn_reservation "ppc601-idiv" 36
; compare executes on integer unit, but feeds insns which
; execute on the branch unit.
(define_insn_reservation "ppc601-compare" 3
- (and (eq_attr "type" "cmp,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,compare,delayed_compare,var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc601"))
"iu_ppc601,nothing,bpu_ppc601")
@@ -58,8 +58,10 @@ (define_insn_reservation "ppc603-storec" 8
"lsu_603")
(define_insn_reservation "ppc603-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ cntlz,exts,isel")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc603"))
"iu_603")
@@ -90,8 +92,10 @@ (define_insn_reservation "ppc603-idiv" 37
"iu_603*37")
(define_insn_reservation "ppc603-compare" 3
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
+ var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc603"))
"iu_603,nothing,bpu_603")
@@ -73,8 +73,10 @@ (define_insn_reservation "ppc630-llsc" 4
"lsu_6xx")
(define_insn_reservation "ppc604-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ cntlz,exts,isel")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
@@ -139,8 +141,10 @@ (define_insn_reservation "ppc620-ldiv" 37
"mciu_6xx*36")
(define_insn_reservation "ppc604-compare" 3
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
+ var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"(iu1_6xx|iu2_6xx)")
@@ -74,8 +74,10 @@ (define_insn_reservation "ppc7450-sync" 35
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
- trap,var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ trap,cntlz,exts,isel")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
@@ -106,8 +108,10 @@ (define_insn_reservation "ppc7450-idiv" 23
"ppc7450_du,mciu_7450*23")
(define_insn_reservation "ppc7450-compare" 2
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
+ var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
@@ -64,8 +64,10 @@ (define_insn_reservation "ppc750-storec" 8
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
- trap,var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ trap,cntlz,exts,isel")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")
@@ -100,8 +102,10 @@ (define_insn_reservation "ppc750-idiv" 19
"ppc750_du,iu1_7xx*19")
(define_insn_reservation "ppc750-compare" 2
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
+ var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,(iu1_7xx|iu2_7xx)")
@@ -155,8 +155,9 @@ (define_insn_reservation "cell-vecstore" 1
;; Integer latency is 2 cycles
(define_insn_reservation "cell-integer" 2
- (and (eq_attr "type" "integer,insert_dword,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert_dword,shift,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "cell"))
"slot01,fxu_cell")
@@ -186,17 +187,21 @@ (define_insn_reservation "cell-cmp" 1
;; add, addo, sub, subo, alter cr0, rldcli, rlwinm
(define_insn_reservation "cell-fast-cmp" 2
- (and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\
- var_delayed_compare")
- (eq_attr "cpu" "cell"))
- (eq_attr "cell_micro" "not"))
+ (and (ior (eq_attr "type" "fast_compare,delayed_compare,compare,\
+ var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
+ (eq_attr "cpu" "cell")
+ (eq_attr "cell_micro" "not"))
"slot01,fxu_cell")
(define_insn_reservation "cell-cmp-microcoded" 9
- (and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\
- var_delayed_compare")
- (eq_attr "cpu" "cell"))
- (eq_attr "cell_micro" "always"))
+ (and (ior (eq_attr "type" "fast_compare,delayed_compare,compare,\
+ var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
+ (eq_attr "cpu" "cell")
+ (eq_attr "cell_micro" "always"))
"slot0+slot1,fxu_cell,fxu_cell*7")
;; mulld
@@ -42,8 +42,10 @@ (define_insn_reservation "mpccore-fpload" 2
"lsu_mpc")
(define_insn_reservation "mpccore-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ cntlz,exts,isel")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "mpccore"))
"iu_mpc")
@@ -69,8 +71,10 @@ (define_insn_reservation "mpccore-idiv" 6
"mciu_mpc*6")
(define_insn_reservation "mpccore-compare" 3
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
+ var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "mpccore"))
"iu_mpc,nothing,bpu_mpc")
@@ -185,8 +185,9 @@ (define_insn_reservation "power4-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
- (and (eq_attr "type" "integer,insert_dword,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert_dword,shift,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "power4"))
"iq_power4")
@@ -226,7 +227,9 @@ (define_insn_reservation "power4-cmp" 3
"iq_power4")
(define_insn_reservation "power4-compare" 2
- (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+ (and (ior (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4,iu2_power4)\
@@ -141,8 +141,10 @@ (define_insn_reservation "power5-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power5-integer" 2
- (and (eq_attr "type" "integer,insert_dword,shift,trap,\
- var_shift_rotate,cntlz,exts,isel,popcnt")
+ (and (ior (eq_attr "type" "integer,insert_dword,shift,trap,\
+ cntlz,exts,isel,popcnt")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "power5"))
"iq_power5")
@@ -179,7 +181,9 @@ (define_insn_reservation "power5-cmp" 3
"iq_power5")
(define_insn_reservation "power5-compare" 2
- (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+ (and (ior (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5,iu2_power5")
@@ -261,6 +261,7 @@ (define_bypass 1 "power6-cntlz"
(define_insn_reservation "power6-var-rotate" 4
(and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")
(eq_attr "cpu" "power6"))
"FXU_power6")
@@ -327,7 +328,9 @@ (define_insn_reservation "power6-delayed-compare" 2 ; N/A
"FXU_power6")
(define_insn_reservation "power6-var-delayed-compare" 4
- (and (eq_attr "type" "var_delayed_compare")
+ (and (ior (eq_attr "type" "var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power6"))
"FXU_power6")
@@ -149,8 +149,10 @@ (define_insn_reservation "power7-sync" 11
; FX Unit
(define_insn_reservation "power7-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
- var_shift_rotate,exts,isel,popcnt")
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ exts,isel,popcnt")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
@@ -175,7 +177,9 @@ (define_insn_reservation "power7-cmp" 1
"DU_power7,FXU_power7")
(define_insn_reservation "power7-compare" 2
- (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+ (and (ior (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power7"))
"DU2F_power7,FXU_power7,FXU_power7")
@@ -23467,10 +23467,13 @@ is_cracked_insn (rtx insn)
|| type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
|| type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
|| type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
+ || type == TYPE_VAR_DELAYED_COMPARE
|| type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
|| type == TYPE_IDIV || type == TYPE_LDIV
|| type == TYPE_INSERT_WORD)
return true;
+ if (get_attr_dot (insn) == DOT_YES && type == TYPE_VAR_SHIFT_ROTATE)
+ return true;
}
return false;
@@ -24307,6 +24310,7 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_IDIV:
case TYPE_INSERT_WORD:
case TYPE_DELAYED_COMPARE:
+ case TYPE_VAR_DELAYED_COMPARE:
case TYPE_IMUL_COMPARE:
case TYPE_LMUL_COMPARE:
case TYPE_FPCOMPARE:
@@ -24413,6 +24417,7 @@ insn_must_be_last_in_group (rtx insn)
case TYPE_LMUL:
case TYPE_IDIV:
case TYPE_DELAYED_COMPARE:
+ case TYPE_VAR_DELAYED_COMPARE:
case TYPE_IMUL_COMPARE:
case TYPE_LMUL_COMPARE:
case TYPE_FPCOMPARE:
@@ -46,8 +46,10 @@ (define_insn_reservation "rs64a-llsc" 2
"lsu_rs64")
(define_insn_reservation "rs64a-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ cntlz,exts,isel")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "rs64a"))
"iu_rs64")
@@ -92,8 +94,10 @@ (define_insn_reservation "rs64a-ldiv" 66
"mciu_rs64*66")
(define_insn_reservation "rs64a-compare" 3
- (and (eq_attr "type" "cmp,fast_compare,compare,\
- delayed_compare,var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare,\
+ delayed_compare,var_delayed_compare")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "rs64a"))
"iu_rs64,nothing,bpu_rs64")
@@ -55,7 +55,9 @@ (define_insn_reservation "titan_mulhw" 4
(define_bypass 2 "titan_mulhw" "titan_mulhw")
(define_insn_reservation "titan_fxu_shift_and_rotate" 2
- (and (eq_attr "type" "insert_word,shift,var_shift_rotate,cntlz")
+ (and (ior (eq_attr "type" "insert_word,shift,cntlz")
+ (and (eq_attr "type" "var_shift_rotate")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing*2,titan_fxu_wb")