Message ID | 51AB6680.7010507@efe-gmbh.de |
---|---|
State | Changes Requested, archived |
Delegated to: | David Miller |
Headers | show |
On 06/02/2013 05:36 PM, Jens Renner (EFE) wrote: > This patch sets the protocol selector bits (4:0) of the PHY's MII_ADVERTISE > register (ANAR) when writing ADVERTISE_ALL. The protocol selector bits are > indicating IEEE 803.3u support and are fixed / read-only on some PHYs. Not > setting them correctly on others (like TI DP83630) makes the PHY fall back > to 10M HDX mode which should be avoided. > > Tested for TI DP83630 PHY on Microblaze platform. > > Signed-off-by: Jens Renner <renner@...-gmbh.de> You should probably fix this line too. Thanks, M
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c index aa14d8a..db16a06 100644 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c @@ -963,7 +963,8 @@ static int xemaclite_open(struct net_device *dev) phy_write(lp->phy_dev, MII_CTRL1000, 0); /* Advertise only 10 and 100mbps full/half duplex speeds */ - phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL); + phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL | + ADVERTISE_CSMA); /* Restart auto negotiation */ bmcr = phy_read(lp->phy_dev, MII_BMCR);