From patchwork Sun Jun 2 12:29:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Blanchard X-Patchwork-Id: 248110 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DE0012C0092 for ; Sun, 2 Jun 2013 22:30:05 +1000 (EST) Received: from localhost ([::1]:55936 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uj7QC-0003Di-0A for incoming@patchwork.ozlabs.org; Sun, 02 Jun 2013 08:30:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52791) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uj7Pr-0003CO-BV for qemu-devel@nongnu.org; Sun, 02 Jun 2013 08:29:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Uj7Pp-00045B-R6 for qemu-devel@nongnu.org; Sun, 02 Jun 2013 08:29:43 -0400 Received: from ozlabs.org ([203.10.76.45]:45122) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uj7Pp-00044x-GL; Sun, 02 Jun 2013 08:29:41 -0400 Received: from kryten (ppp121-44-134-28.lns20.syd7.internode.on.net [121.44.134.28]) (using SSLv3 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPSA id 504882C0092; Sun, 2 Jun 2013 22:29:40 +1000 (EST) Date: Sun, 2 Jun 2013 22:29:39 +1000 From: Anton Blanchard To: david@gibson.dropbear.id.au, agraf@suse.de, rth@twiddle.net, aurelien@aurel32.net Message-ID: <20130602222939.05c513a3@kryten> In-Reply-To: <20130602222452.1b0fdbd1@kryten> References: <20130602222452.1b0fdbd1@kryten> X-Mailer: Claws Mail 3.8.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Mime-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 203.10.76.45 Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 3/4] tcg-ppc64: Fix add2_i64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org add2_i64 was adding the lower double word to the upper double word of each input. Fix this so we add the lower double words, then the upper double words with carry propagation. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard Reviewed-by: Richard Henderson --- sub2 has similar issues, I haven't fixed it because I don't have a testcase yet. Index: b/tcg/ppc64/tcg-target.c =================================================================== --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1958,18 +1958,18 @@ static void tcg_out_op (TCGContext *s, T environment. So in 64-bit mode it's always carry-out of bit 63. The fallback code using deposit works just as well for 32-bit. */ a0 = args[0], a1 = args[1]; - if (a0 == args[4] || (!const_args[5] && a0 == args[5])) { + if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { a0 = TCG_REG_R0; } - if (const_args[3]) { - tcg_out32(s, ADDIC | TAI(a0, args[2], args[3])); + if (const_args[4]) { + tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); } else { - tcg_out32(s, ADDC | TAB(a0, args[2], args[3])); + tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); } if (const_args[5]) { - tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[4])); + tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); } else { - tcg_out32(s, ADDE | TAB(a1, args[4], args[5])); + tcg_out32(s, ADDE | TAB(a1, args[3], args[5])); } if (a0 != args[0]) { tcg_out_mov(s, TCG_TYPE_I64, args[0], a0); @@ -2147,7 +2147,7 @@ static const TCGTargetOpDef ppc_op_defs[ { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, { INDEX_op_deposit_i64, { "r", "0", "rZ" } }, - { INDEX_op_add2_i64, { "r", "r", "r", "rI", "r", "rZM" } }, + { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } }, { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } }, { INDEX_op_muls2_i64, { "r", "r", "r", "r" } }, { INDEX_op_mulu2_i64, { "r", "r", "r", "r" } },