From patchwork Thu May 30 15:56:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksandr Dmytryshyn X-Patchwork-Id: 247635 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8B41F2C0092 for ; Fri, 31 May 2013 01:56:27 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757536Ab3E3P40 (ORCPT ); Thu, 30 May 2013 11:56:26 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:33196 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756361Ab3E3P4Z (ORCPT ); Thu, 30 May 2013 11:56:25 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r4UFuMds031313; Thu, 30 May 2013 10:56:22 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r4UFuMcj013855; Thu, 30 May 2013 10:56:22 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Thu, 30 May 2013 10:56:22 -0500 Received: from localhost (uglx0170755.ucm2.emeaucm.ext.ti.com [10.167.145.67]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r4UFuLhS024969; Thu, 30 May 2013 10:56:22 -0500 From: Oleksandr Dmytryshyn To: Tony Lindgren , Wolfram Sang CC: , , Subject: [PATCH v2 1/1] i2c: omap: correct usage of the interrupt enable register Date: Thu, 30 May 2013 18:56:19 +0300 Message-ID: <1369929379-19165-2-git-send-email-oleksandr.dmytryshyn@ti.com> X-Mailer: git-send-email 1.8.2.rc2 In-Reply-To: <1369929379-19165-1-git-send-email-oleksandr.dmytryshyn@ti.com> References: <1369929379-19165-1-git-send-email-oleksandr.dmytryshyn@ti.com> MIME-Version: 1.0 Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org If the i2c controller during suspend will generate an interrupt, it can lead to unpredictable behaviour in the kernel. Based on the logic of the kernel code interrupts from i2c should be prohibited during suspend. Kernel writes 0 to the I2C_IE register in the omap_i2c_runtime_suspend() function. In the other side kernel writes saved interrupt flags to the I2C_IE register in omap_i2c_runtime_resume() function. I.e. interrupts should be disabled during suspend. This works for chips with version1 registers scheme. Interrupts are disabled during suspend. For chips with version2 scheme registers writting 0 to the I2C_IE register does nothing (because now the I2C_IRQENABLE_SET register is located at this address). This register is used to enable interrupts. For disabling interrupts I2C_IRQENABLE_CLR register should be used. Because the registers I2C_IRQENABLE_SET and I2C_IE have the same addresses, the interrupt enabling procedure is unchanged. Signed-off-by: Oleksandr Dmytryshyn --- drivers/i2c/busses/i2c-omap.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index e02f9e3..2419899 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -180,6 +180,8 @@ enum { #define I2C_OMAP_ERRATA_I207 (1 << 0) #define I2C_OMAP_ERRATA_I462 (1 << 1) +#define OMAP_I2C_INTERRUPTS_MASK 0x6FFF + struct omap_i2c_dev { spinlock_t lock; /* IRQ synchronization */ struct device *dev; @@ -193,6 +195,7 @@ struct omap_i2c_dev { long latency); u32 speed; /* Speed of bus in kHz */ u32 flags; + u16 scheme; u16 cmd_err; u8 *buf; u8 *regs; @@ -1082,7 +1085,7 @@ omap_i2c_probe(struct platform_device *pdev) int irq; int r; u32 rev; - u16 minor, major, scheme; + u16 minor, major; /* NOTE: driver uses the static register mapping */ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -1159,8 +1162,8 @@ omap_i2c_probe(struct platform_device *pdev) */ rev = __raw_readw(dev->base + 0x04); - scheme = OMAP_I2C_SCHEME(rev); - switch (scheme) { + dev->scheme = OMAP_I2C_SCHEME(rev); + switch (dev->scheme) { case OMAP_I2C_SCHEME_0: dev->regs = (u8 *)reg_map_ip_v1; dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG); @@ -1289,7 +1292,11 @@ static int omap_i2c_runtime_suspend(struct device *dev) _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); - omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); + if (_dev->scheme == OMAP_I2C_SCHEME_0) + omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); + else + omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, + OMAP_I2C_INTERRUPTS_MASK); if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */