From patchwork Thu May 30 11:32:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Bolton X-Patchwork-Id: 247547 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 8B4CB2C007C for ; Thu, 30 May 2013 21:33:16 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:references:in-reply-to:subject:date:message-id:mime-version :content-type; q=dns; s=default; b=GfCL1dvm7JS9TB5+QybJOk6kHXoln hm0cC95C0ulh6Hin/zAOHVodMQ3WBkw+Ex04HCszEsHCxPrEg7NVLmKnpX2veZi1 UMoReFO+DF1KE1XsqHZa4ZyUkdOt5GxFyfkzB8NiYfARgo0vaGTzpSo2QKCre3Al /8mYzps8BfI0Gs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:references:in-reply-to:subject:date:message-id:mime-version :content-type; s=default; bh=xpaSQ1pkdqsp4dkqulJSCJrd7KU=; b=lo6 979GHckUw6mZlZ5F7vsCCuGc+Y6G2W6A0fUV2r7DUr/bm7OzRs3yF7rhbcUZNy2x 9lCljS8w1+T1Nvyqqi5g0BS0FHllGedYHkr9bfGiuYFdZcTUQQruuHeo2YpVCIYC MHqP8yQtPysPDsHTiCpTlg3u8a3epjnswPRsVRpQ= Received: (qmail 14717 invoked by alias); 30 May 2013 11:33:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 14682 invoked by uid 89); 30 May 2013 11:33:02 -0000 X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, KHOP_THREADED, MSGID_MULTIPLE_AT, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Thu, 30 May 2013 11:33:00 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 30 May 2013 12:32:58 +0100 Received: from E102352xp ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 30 May 2013 12:32:56 +0100 From: "Ian Bolton" To: "'Richard Henderson'" , References: <000101ce4bd2$6f17d010$4d477030$@bolton@arm.com> <000401ce558b$9a28bfe0$ce7a3fa0$@bolton@arm.com> <519A7B48.8060608@redhat.com> In-Reply-To: <519A7B48.8060608@redhat.com> Subject: RE: [PATCH, AArch64] Support BFI instruction and insv standard pattern Date: Thu, 30 May 2013 12:32:36 +0100 Message-ID: <000401ce5d29$62bf4e70$283deb50$@bolton@arm.com> MIME-Version: 1.0 X-MC-Unique: 113053012325800201 X-Virus-Found: No > On 05/20/2013 11:55 AM, Ian Bolton wrote: > > I improved this patch during the work I did on the recent insv_imm > patch > > (http://gcc.gnu.org/ml/gcc-patches/2013-05/msg01007.html). > > Thanks, you cleaned up almost everything on which I would have > commented > with the previous patch revision. The only thing left is: > > > + else if (!register_operand (value, mode)) > > + operands[3] = force_reg (mode, value); > > Checking register_operand before force_reg is unnecessary; you're not > saving a > function call, and force_reg will itself perform the register check. Thanks for the review, Richard. Latest patch is attached, which fixes this. Linux and bare-metal regression runs successful. OK for trunk? Cheers, Ian 2013-05-30 Ian Bolton gcc/ * config/aarch64/aarch64.md (insv): New define_expand. (*insv_reg): New define_insn. testsuite/ * gcc.target/aarch64/insv_1.c: New test. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 2bdbfa9..89db092 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3163,6 +3163,50 @@ (set_attr "mode" "")] ) +;; Bitfield Insert (insv) +(define_expand "insv" + [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand") + (match_operand 1 "const_int_operand") + (match_operand 2 "const_int_operand")) + (match_operand:GPI 3 "general_operand"))] + "" +{ + unsigned HOST_WIDE_INT width = UINTVAL (operands[1]); + unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); + rtx value = operands[3]; + + if (width == 0 || (pos + width) > GET_MODE_BITSIZE (mode)) + FAIL; + + if (CONST_INT_P (value)) + { + unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT)1 << width) - 1; + + /* Prefer AND/OR for inserting all zeros or all ones. */ + if ((UINTVAL (value) & mask) == 0 + || (UINTVAL (value) & mask) == mask) + FAIL; + + /* 16-bit aligned 16-bit wide insert is handled by insv_imm. */ + if (width == 16 && (pos % 16) == 0) + DONE; + } + operands[3] = force_reg (mode, value); +}) + +(define_insn "*insv_reg" + [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") + (match_operand 1 "const_int_operand" "n") + (match_operand 2 "const_int_operand" "n")) + (match_operand:GPI 3 "register_operand" "r"))] + "!(UINTVAL (operands[1]) == 0 + || (UINTVAL (operands[2]) + UINTVAL (operands[1]) + > GET_MODE_BITSIZE (mode)))" + "bfi\\t%0, %3, %2, %1" + [(set_attr "v8type" "bfm") + (set_attr "mode" "")] +) + (define_insn "*_shft_" [(set (match_operand:GPI 0 "register_operand" "=r") (ashift:GPI (ANY_EXTEND:GPI diff --git a/gcc/testsuite/gcc.target/aarch64/insv_1.c b/gcc/testsuite/gcc.target/aarch64/insv_1.c new file mode 100644 index 0000000..bc8928d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/insv_1.c @@ -0,0 +1,84 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ + +extern void abort (void); + +typedef struct bitfield +{ + unsigned short eight: 8; + unsigned short four: 4; + unsigned short five: 5; + unsigned short seven: 7; + unsigned int sixteen: 16; +} bitfield; + +bitfield +bfi1 (bitfield a) +{ + /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 0, 8" } } */ + a.eight = 3; + return a; +} + +bitfield +bfi2 (bitfield a) +{ + /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 16, 5" } } */ + a.five = 7; + return a; +} + +bitfield +movk (bitfield a) +{ + /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 32" } } */ + a.sixteen = 7531; + return a; +} + +bitfield +set1 (bitfield a) +{ + /* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 2031616" } } */ + a.five = 0x1f; + return a; +} + +bitfield +set0 (bitfield a) +{ + /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -2031617" } } */ + a.five = 0; + return a; +} + + +int +main (int argc, char** argv) +{ + static bitfield a; + bitfield b = bfi1 (a); + bitfield c = bfi2 (b); + bitfield d = movk (c); + + if (d.eight != 3) + abort (); + + if (d.five != 7) + abort (); + + if (d.sixteen != 7531) + abort (); + + d = set1 (d); + if (d.five != 0x1f) + abort (); + + d = set0 (d); + if (d.five != 0) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */