From patchwork Wed May 29 11:02:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 247236 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AF8982C0209 for ; Wed, 29 May 2013 21:04:22 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6BE334A04F; Wed, 29 May 2013 13:04:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id peHTjZ0CUczA; Wed, 29 May 2013 13:04:02 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2C45F4A050; Wed, 29 May 2013 13:03:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 10AA64A03B for ; Wed, 29 May 2013 13:03:12 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VxJk2FTlcAQr for ; Wed, 29 May 2013 13:03:06 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id 44B234A026 for ; Wed, 29 May 2013 13:02:54 +0200 (CEST) Received: from dbdlxv05.itg.ti.com ([172.24.171.60]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r4TB2ph8020560 for ; Wed, 29 May 2013 06:02:52 -0500 Received: from DBDE72.ent.ti.com (dbde72.ent.ti.com [172.24.171.97]) by dbdlxv05.itg.ti.com (8.14.3/8.13.8) with ESMTP id r4TB2mTM024265 for ; Wed, 29 May 2013 06:02:50 -0500 Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE72.ent.ti.com (172.24.171.97) with Microsoft SMTP Server id 14.2.342.3; Wed, 29 May 2013 19:02:48 +0800 Received: from a0131933lt.apr.dhcp.ti.com (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id r4TB2ltG031159; Wed, 29 May 2013 16:32:47 +0530 From: Lokesh Vutla To: Date: Wed, 29 May 2013 16:32:37 +0530 Message-ID: <1369825367-4537-3-git-send-email-lokeshvutla@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1369825367-4537-1-git-send-email-lokeshvutla@ti.com> References: <1369825367-4537-1-git-send-email-lokeshvutla@ti.com> MIME-Version: 1.0 Cc: trini@ti.com, rnayak@ti.com Subject: [U-Boot] [PATCH 02/12] ARM: DRA7xx: power Add support for tps659038 PMIC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards. Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 23 ++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 38 +++++++++++++++++++++++- arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + arch/arm/include/asm/arch-omap5/clocks.h | 15 ++++++++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/omap_common.h | 3 ++ 6 files changed, 80 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 0daf98c..c51c359 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -30,6 +30,7 @@ * MA 02111-1307 USA */ #include +#include #include #include #include @@ -487,6 +488,9 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) u32 offset = volt_mv; int ret = 0; + if (!volt_mv) + return; + pmic->pmic_bus_init(); /* See if we can first get the GPIO if needed */ if (pmic->gpio_en) @@ -534,6 +538,15 @@ void scale_vcores(struct vcores_data const *vcores) do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic); + do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, + vcores->gpu.pmic); + + do_scale_vcore(vcores->eve.addr, vcores->eve.value, + vcores->eve.pmic); + + do_scale_vcore(vcores->iva.addr, vcores->iva.value, + vcores->iva.pmic); + if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { /* Configure LDO SRAM "magic" bits */ writel(2, (*prcm)->prm_sldo_core_setup); @@ -723,3 +736,13 @@ void prcm_init(void) if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) enable_basic_uboot_clocks(); } + +void gpi2c_init(void) +{ + static int gpi2c = 1; + + if (gpi2c) { + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + gpi2c = 0; + } +} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 74e473d..e9d34c1 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -26,6 +26,7 @@ * MA 02111-1307 USA */ #include +#include #include #include #include @@ -294,6 +295,19 @@ struct pmic_data palmas = { .pmic_write = omap_vc_bypass_send_value, }; +struct pmic_data tps659038 = { + .base_offset = PALMAS_SMPS_BASE_VOLT_UV, + .step = 10000, /* 10 mV represented in uV */ + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + .start_code = 6, + .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, + .pmic_bus_init = gpi2c_init, + .pmic_write = palmas_i2c_write_u8, +}; + struct vcores_data omap5430_volts = { .mpu.value = VDD_MPU, .mpu.addr = SMPS_REG_ADDR_12_MPU, @@ -322,6 +336,28 @@ struct vcores_data omap5430_volts_es2 = { .mm.pmic = &palmas, }; +struct vcores_data dra752_volts = { + .mpu.value = VDD_MPU_DRA752, + .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, + .mpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA752, + .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, + .eve.pmic = &tps659038, + + .gpu.value = VDD_GPU_DRA752, + .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, + .gpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA752, + .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA752, + .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, + .iva.pmic = &tps659038, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -562,7 +598,7 @@ void hw_data_init(void) case DRA752_ES1_0: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; - *omap_vcores = &omap5430_volts_es2; + *omap_vcores = &dra752_volts; *ctrl = &dra7xx_ctrl; break; diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 37d6c69..438cb96 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -57,6 +57,7 @@ u32 cortex_rev(void); void init_omap_revision(void); void do_io_settings(void); void sri2c_init(void); +void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index ca75f63..b43737e 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -212,9 +212,24 @@ #define VDD_MPU_ES2_LOW 880 #define VDD_MM_ES2_LOW 880 +/* TPS659038 Voltage settings in mv for OPP_NOMINAL */ +#define VDD_MPU_DRA752 1090 +#define VDD_EVE_DRA752 1060 +#define VDD_GPU_DRA752 1060 +#define VDD_CORE_DRA752 1030 +#define VDD_IVA_DRA752 1060 + /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 +/* TPS659038 */ +#define TPS659038_I2C_SLAVE_ADDR 0x58 +#define TPS659038_REG_ADDR_SMPS12_MPU 0x23 +#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B +#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F +#define TPS659038_REG_ADDR_SMPS7_CORE 0x33 +#define TPS659038_REG_ADDR_SMPS8_IVA 0x37 + /* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 #define TPS62361_REG_ADDR_SET0 0x0 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 32ced5f..36cfc6f 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -61,6 +61,7 @@ u32 cortex_rev(void); void init_omap_revision(void); void do_io_settings(void); void sri2c_init(void); +void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 3f1d31d..6b28f2e 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -510,6 +510,9 @@ struct vcores_data { struct volts mpu; struct volts core; struct volts mm; + struct volts gpu; + struct volts eve; + struct volts iva; }; extern struct prcm_regs const **prcm;