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PCI: fix trivial typo for PCI_EXP_LNKCAP_CLKPM

Message ID 1369818112-33136-1-git-send-email-wangyijing@huawei.com
State Accepted
Headers show

Commit Message

Yijing Wang May 29, 2013, 9:01 a.m. UTC
Fix trivial typo for PCI_EXP_LNKCAP_CLKPM comment.

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
---
 include/uapi/linux/pci_regs.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Comments

Bjorn Helgaas May 29, 2013, 8:49 p.m. UTC | #1
On Wed, May 29, 2013 at 05:01:52PM +0800, Yijing Wang wrote:
> Fix trivial typo for PCI_EXP_LNKCAP_CLKPM comment.
> 
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
> ---
>  include/uapi/linux/pci_regs.h |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)

Applied to pci/misc for v3.11, thanks!

> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 864e324..c3cc01d 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -468,7 +468,7 @@
>  #define  PCI_EXP_LNKCAP_ASPMS	0x00000c00 /* ASPM Support */
>  #define  PCI_EXP_LNKCAP_L0SEL	0x00007000 /* L0s Exit Latency */
>  #define  PCI_EXP_LNKCAP_L1EL	0x00038000 /* L1 Exit Latency */
> -#define  PCI_EXP_LNKCAP_CLKPM	0x00040000 /* L1 Clock Power Management */
> +#define  PCI_EXP_LNKCAP_CLKPM	0x00040000 /* Clock Power Management */
>  #define  PCI_EXP_LNKCAP_SDERC	0x00080000 /* Surprise Down Error Reporting Capable */
>  #define  PCI_EXP_LNKCAP_DLLLARC	0x00100000 /* Data Link Layer Link Active Reporting Capable */
>  #define  PCI_EXP_LNKCAP_LBNC	0x00200000 /* Link Bandwidth Notification Capability */
> -- 
> 1.7.1
> 
> 
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diff mbox

Patch

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 864e324..c3cc01d 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -468,7 +468,7 @@ 
 #define  PCI_EXP_LNKCAP_ASPMS	0x00000c00 /* ASPM Support */
 #define  PCI_EXP_LNKCAP_L0SEL	0x00007000 /* L0s Exit Latency */
 #define  PCI_EXP_LNKCAP_L1EL	0x00038000 /* L1 Exit Latency */
-#define  PCI_EXP_LNKCAP_CLKPM	0x00040000 /* L1 Clock Power Management */
+#define  PCI_EXP_LNKCAP_CLKPM	0x00040000 /* Clock Power Management */
 #define  PCI_EXP_LNKCAP_SDERC	0x00080000 /* Surprise Down Error Reporting Capable */
 #define  PCI_EXP_LNKCAP_DLLLARC	0x00100000 /* Data Link Layer Link Active Reporting Capable */
 #define  PCI_EXP_LNKCAP_LBNC	0x00200000 /* Link Bandwidth Notification Capability */