Patchwork [U-Boot,v4,09/10] NET: mvgbe: add support for Dove

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Submitter Sascha Silbe
Date May 26, 2013, 6:37 p.m.
Message ID <1369593423-19763-10-git-send-email-t-uboot@infra-silbe.de>
Download mbox | patch
Permalink /patch/246466/
State Superseded
Delegated to: Prafulla Wadaskar
Headers show

Comments

Sascha Silbe - May 26, 2013, 6:37 p.m.
From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
---
 v3->v4: removed EBAR_DRAM_CS* for Dove

 drivers/net/mvgbe.c | 9 ++++++++-
 drivers/net/mvgbe.h | 2 ++
 2 files changed, 10 insertions(+), 1 deletion(-)

Patch

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 7f0ddf5..57692e3 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -43,6 +43,8 @@ 
 #include <asm/arch/kirkwood.h>
 #elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
+#elif defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
 #endif
 
 #include "mvgbe.h"
@@ -286,7 +288,11 @@  static void set_dram_access(struct mvgbe_registers *regs)
 		else
 			win_param.enable = 1;	/* Enable the access */
 
-		/* Enable DRAM bank */
+#ifdef CONFIG_DOVE
+		/* Choose DRAM as target */
+		win_param.attrib = 0;
+#else
+		/* Choose one DRAM bank (chip select line) as target */
 		switch (i) {
 		case 0:
 			win_param.attrib = EBAR_DRAM_CS0;
@@ -306,6 +312,7 @@  static void set_dram_access(struct mvgbe_registers *regs)
 			win_param.attrib = 0;
 			break;
 		}
+#endif
 		/* Set the access control for address window(EPAPR) RD/WR */
 		set_access_control(regs, &win_param);
 	}
diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index d8a5429..22b571e 100644
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -308,10 +308,12 @@ 
 #define EBAR_TARGET_GUNIT			0x00000007
 
 /* Window attrib */
+#if !defined(CONFIG_DOVE)
 #define EBAR_DRAM_CS0				0x00000E00
 #define EBAR_DRAM_CS1				0x00000D00
 #define EBAR_DRAM_CS2				0x00000B00
 #define EBAR_DRAM_CS3				0x00000700
+#endif
 
 /* DRAM Target interface */
 #define EBAR_DRAM_NO_CACHE_COHERENCY		0x00000000