From patchwork Sun May 26 18:37:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Silbe X-Patchwork-Id: 246462 X-Patchwork-Delegate: prafulla@marvell.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A419E2C0296 for ; Mon, 27 May 2013 06:50:45 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0406A4A0A1; Sun, 26 May 2013 22:50:19 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sIFp2mDq7oTR; Sun, 26 May 2013 22:50:18 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AD0154A030; Sun, 26 May 2013 22:49:51 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C4C424A01C for ; Sun, 26 May 2013 20:42:53 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id A+JU3iqmsL5j for ; Sun, 26 May 2013 20:42:52 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from b.mx.chost.de (setoy2.chost.de [87.106.8.89]) by theia.denx.de (Postfix) with ESMTPS id 373A24A025 for ; Sun, 26 May 2013 20:42:45 +0200 (CEST) Received: from sshgate.chost.de (sshgate.chost.de [::ffff:87.106.80.19]) by b.mx.chost.de with esmtp; Sun, 26 May 2013 20:37:39 +0200 id 0EF4FC62.51A25673.000003EC Received: by sshgate.chost.de (sSMTP sendmail emulation); Sun, 26 May 2013 20:37:39 +0200 Received: (nullmailer pid 20142 invoked by uid 8193); Sun, 26 May 2013 18:37:31 -0000 From: Sascha Silbe To: u-boot@lists.denx.de Date: Sun, 26 May 2013 20:37:01 +0200 Message-Id: <1369593423-19763-9-git-send-email-t-uboot@infra-silbe.de> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1369593423-19763-1-git-send-email-t-uboot@infra-silbe.de> References: <1369593423-19763-1-git-send-email-t-uboot@infra-silbe.de> X-Mailman-Approved-At: Sun, 26 May 2013 22:49:45 +0200 Cc: Rabeeh Khoury , Luka Perkov , Daniel Stodden , Andy Fleming Subject: [U-Boot] [PATCH v4 08/10] NET: mvgbe: add phylib support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Sebastian Hesselbarth This add phylib support to the Marvell GBE driver. Signed-off-by: Sebastian Hesselbarth Acked-by: Prafulla Wadaskar Signed-off-by: Sascha Silbe Acked-by: Prafulla Wadaskar --- v3->v4: avoided unused variable warning; made checkpatch clean drivers/net/mvgbe.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 68 insertions(+), 6 deletions(-) diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 47bf27c..7f0ddf5 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -52,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR; #define MV_PHY_ADR_REQUEST 0xee #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* * smi_reg_read - miiphy_read callback function. * @@ -184,6 +184,25 @@ static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) } #endif +#if defined(CONFIG_PHYLIB) +int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr) +{ + u16 data; + int ret; + ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data); + if (ret) + return ret; + return data; +} + +int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr, u16 data) +{ + return smi_reg_write(bus->name, phy_addr, reg_addr, data); +} +#endif + /* Stop and checks all queues */ static void stop_queue(u32 * qreg) { @@ -415,8 +434,9 @@ static int mvgbe_init(struct eth_device *dev) { struct mvgbe_device *dmvgbe = to_mvgbe(dev); struct mvgbe_registers *regs = dmvgbe->regs; -#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ - && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ + !defined(CONFIG_PHYLIB) && \ + defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) int i; #endif /* setup RX rings */ @@ -467,8 +487,9 @@ static int mvgbe_init(struct eth_device *dev) /* Enable port Rx. */ MVGBE_REG_WR(regs->rqc, (1 << RXUQ)); -#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ - && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ + !defined(CONFIG_PHYLIB) && \ + defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) /* Wait up to 5s for the link status */ for (i = 0; i < 5; i++) { u16 phyadr; @@ -647,6 +668,45 @@ static int mvgbe_recv(struct eth_device *dev) return 0; } +#if defined(CONFIG_PHYLIB) +int mvgbe_phylib_init(struct eth_device *dev, int phyid) +{ + struct mii_dev *bus; + struct phy_device *phydev; + int ret; + + bus = mdio_alloc(); + if (!bus) { + printf("mdio_alloc failed\n"); + return -ENOMEM; + } + bus->read = mvgbe_phy_read; + bus->write = mvgbe_phy_write; + sprintf(bus->name, dev->name); + + ret = mdio_register(bus); + if (ret) { + printf("mdio_register failed\n"); + free(bus); + return -ENOMEM; + } + + /* Set phy address of the port */ + mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid); + + phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + printf("phy_connect failed\n"); + return -ENODEV; + } + + phy_config(phydev); + phy_startup(phydev); + + return 0; +} +#endif + int mvgbe_initialize(bd_t *bis) { struct mvgbe_device *dmvgbe; @@ -729,7 +789,9 @@ error1: eth_register(dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_PHYLIB) + mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum); +#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, smi_reg_read, smi_reg_write); /* Set phy address of the port */ miiphy_write(dev->name, MV_PHY_ADR_REQUEST,