From patchwork Sun May 26 02:56:31 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 246364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 105D32C0089 for ; Sun, 26 May 2013 13:05:32 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758873Ab3EZDFb (ORCPT ); Sat, 25 May 2013 23:05:31 -0400 Received: from gnurou.org ([207.192.72.5]:55613 "EHLO mail.gnurou.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758869Ab3EZDFa (ORCPT ); Sat, 25 May 2013 23:05:30 -0400 X-Greylist: delayed 525 seconds by postgrey-1.27 at vger.kernel.org; Sat, 25 May 2013 23:05:30 EDT Received: from localhost.localdomain (softbank126010191003.bbtec.net [126.10.191.3]) by mail.gnurou.org (Postfix) with ESMTPSA id 843CD301DA; Sun, 26 May 2013 11:58:15 +0900 (JST) From: Alexandre Courbot To: Mike Turquette , Stephen Warren , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, gnurou@gmail.com, Alexandre Courbot Subject: [PATCH RESEND] ARM: tegra114: correctly output clk_32k Date: Sun, 26 May 2013 11:56:31 +0900 Message-Id: <1369536991-6111-1-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 1.8.2.3 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra has a blink timer register that allows to modulate the clk_32k clock before outputting it. Since clk_32k is presented to the kernel as a fixed clock, make sure this register does not tamper with the clock frequency and that clk_32k is outputted as-is, similarly to what is done on t20 and t30. Signed-off-by: Alexandre Courbot Acked-by: Stephen Warren --- drivers/clk/tegra/clk-tegra114.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index d78e16e..dc76d67 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -127,6 +127,7 @@ #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 #define PMC_CTRL 0 #define PMC_CTRL_BLINK_ENB 7 +#define PMC_BLINK_TIMER 0x40 #define OSC_CTRL 0x50 #define OSC_CTRL_OSC_FREQ_SHIFT 28 @@ -1625,6 +1626,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) clks[clk_out_3] = clk; /* blink */ + /* clear the blink timer register to directly output clk_32k */ + writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, pmc_base + PMC_DPD_PADS_ORIDE, PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);