From patchwork Thu May 23 14:32:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 245959 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2C5B02C0299 for ; Fri, 24 May 2013 00:33:23 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758797Ab3EWOdV (ORCPT ); Thu, 23 May 2013 10:33:21 -0400 Received: from mail.free-electrons.com ([94.23.35.102]:45257 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758002Ab3EWOdU (ORCPT ); Thu, 23 May 2013 10:33:20 -0400 Received: by mail.free-electrons.com (Postfix, from userid 106) id 22061BB7; Thu, 23 May 2013 16:33:19 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.3.2 Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 5372F1638; Thu, 23 May 2013 16:32:59 +0200 (CEST) From: Thomas Petazzoni To: Bjorn Helgaas , linux-pci@vger.kernel.org, Jason Cooper , Andrew Lunn , Gregory Clement Cc: Ezequiel Garcia , Lior Amsalem , linux-arm-kernel@lists.infradead.org, Maen Suleiman Subject: [PATCH v2 3/3] pci: mvebu: fix the emulation of the status register Date: Thu, 23 May 2013 16:32:53 +0200 Message-Id: <1369319573-19927-4-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1369319573-19927-1-git-send-email-thomas.petazzoni@free-electrons.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The status register of the PCI configuration space of PCI-to-PCI bridges contain some read-only bits, and so write-1-to-clear bits. So, the Linux PCI core sometimes writes 0xffff to this status register, and in the current PCI-to-PCI bridge emulation code of the Marvell driver, we do take all those 1s being written. Even the read-only bits are being overwritten. For now, all the read-only bits should be emulated to have the zero value. The other bits, that are write-1-to-clear bits are used to report various kind of errors, and are never set by the emulated bridge, so there is no need to support this write-1-to-clear bits mechanism. As a conclusion, the easiest solution is to simply emulate this status register by returning zero when read, and ignore the writes to it. This has two visible effects: * The devsel is no longer 'unknown' in, i.e Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0 becomes: Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0 in lspci -v. This was caused by a value of 11b being read for devsel, which is an invalid value. This 11b value being read was due to a previous write of 0xffff into the status register. * The capability list is no longer broken, because we indicate to the Linux PCI core that we don't have a Capabilities Pointer in the PCI configuration space of this bridge. The following message is therefore no longer visible in lspci -v: Capabilities: [fc] Signed-off-by: Thomas Petazzoni --- drivers/pci/host/pci-mvebu.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c index a3c4638..481e44a 100644 --- a/drivers/pci/host/pci-mvebu.c +++ b/drivers/pci/host/pci-mvebu.c @@ -69,7 +69,6 @@ struct mvebu_sw_pci_bridge { u16 vendor; u16 device; u16 command; - u16 status; u16 class; u8 interface; u8 revision; @@ -359,7 +358,6 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port) memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); - bridge->status = PCI_STATUS_CAP_LIST; bridge->class = PCI_CLASS_BRIDGE_PCI; bridge->vendor = PCI_VENDOR_ID_MARVELL; bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID; @@ -386,7 +384,7 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, break; case PCI_COMMAND: - *value = bridge->status << 16 | bridge->command; + *value = bridge->command; break; case PCI_CLASS_REVISION: @@ -479,7 +477,6 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, switch (where & ~3) { case PCI_COMMAND: bridge->command = value & 0xffff; - bridge->status = value >> 16; break; case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: