Patchwork [4/5] x86, perf: Add conditional branch filtering support

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Submitter Anshuman Khandual
Date May 22, 2013, 6:22 a.m.
Message ID <1369203761-12649-5-git-send-email-khandual@linux.vnet.ibm.com>
Download mbox | patch
Permalink /patch/245543/
State Not Applicable
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Comments

Anshuman Khandual - May 22, 2013, 6:22 a.m.
From: Peter Zijlstra <a.p.zijlstra@chello.nl>

This patch adds conditional branch filtering support,
enabling it for PERF_SAMPLE_BRANCH_COND in perf branch
stack sampling framework by utilizing an available
software filter X86_BR_JCC.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/x86/kernel/cpu/perf_event_intel_lbr.c | 6 ++++++
 1 file changed, 6 insertions(+)
Stephane Eranian - May 23, 2013, 1:38 p.m.
On Wed, May 22, 2013 at 8:22 AM, Anshuman Khandual
<khandual@linux.vnet.ibm.com> wrote:
> From: Peter Zijlstra <a.p.zijlstra@chello.nl>
>
> This patch adds conditional branch filtering support,
> enabling it for PERF_SAMPLE_BRANCH_COND in perf branch
> stack sampling framework by utilizing an available
> software filter X86_BR_JCC.
>
Reviewed-by: Stephane Eranian <eranian@google.com>

> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
> ---
>  arch/x86/kernel/cpu/perf_event_intel_lbr.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> index d978353..a0d6387 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> @@ -337,6 +337,10 @@ static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
>
>         if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
>                 mask |= X86_BR_IND_CALL;
> +
> +       if (br_type & PERF_SAMPLE_BRANCH_COND)
> +               mask |= X86_BR_JCC;
> +
>         /*
>          * stash actual user request into reg, it may
>          * be used by fixup code for some CPU
> @@ -626,6 +630,7 @@ static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
>          * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
>          */
>         [PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL | LBR_IND_JMP,
> +       [PERF_SAMPLE_BRANCH_COND]     = LBR_JCC,
>  };
>
>  static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
> @@ -637,6 +642,7 @@ static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
>         [PERF_SAMPLE_BRANCH_ANY_CALL]   = LBR_REL_CALL | LBR_IND_CALL
>                                         | LBR_FAR,
>         [PERF_SAMPLE_BRANCH_IND_CALL]   = LBR_IND_CALL,
> +       [PERF_SAMPLE_BRANCH_COND]       = LBR_JCC,
>  };
>
>  /* core */
> --
> 1.7.11.7
>

Patch

diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index d978353..a0d6387 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -337,6 +337,10 @@  static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
 
 	if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
 		mask |= X86_BR_IND_CALL;
+
+	if (br_type & PERF_SAMPLE_BRANCH_COND)
+		mask |= X86_BR_JCC;
+
 	/*
 	 * stash actual user request into reg, it may
 	 * be used by fixup code for some CPU
@@ -626,6 +630,7 @@  static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
 	 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
 	 */
 	[PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL | LBR_IND_JMP,
+	[PERF_SAMPLE_BRANCH_COND]     = LBR_JCC,
 };
 
 static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
@@ -637,6 +642,7 @@  static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
 	[PERF_SAMPLE_BRANCH_ANY_CALL]	= LBR_REL_CALL | LBR_IND_CALL
 					| LBR_FAR,
 	[PERF_SAMPLE_BRANCH_IND_CALL]	= LBR_IND_CALL,
+	[PERF_SAMPLE_BRANCH_COND]	= LBR_JCC,
 };
 
 /* core */