From patchwork Wed May 22 05:33:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hu Tao X-Patchwork-Id: 245519 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 70E152C00A2 for ; Wed, 22 May 2013 15:38:52 +1000 (EST) Received: from localhost ([::1]:43813 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uf1lC-0000Dq-AK for incoming@patchwork.ozlabs.org; Wed, 22 May 2013 01:38:50 -0400 Received: from eggs.gnu.org ([208.118.235.92]:58606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uf1h4-0002ZP-9u for qemu-devel@nongnu.org; Wed, 22 May 2013 01:34:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Uf1gv-000064-7x for qemu-devel@nongnu.org; Wed, 22 May 2013 01:34:34 -0400 Received: from [222.73.24.84] (port=12267 helo=song.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uf1gu-0008RJ-JM for qemu-devel@nongnu.org; Wed, 22 May 2013 01:34:25 -0400 X-IronPort-AV: E=Sophos;i="4.87,719,1363104000"; d="scan'208";a="7330834" Received: from unknown (HELO tang.cn.fujitsu.com) ([10.167.250.3]) by song.cn.fujitsu.com with ESMTP; 22 May 2013 13:31:14 +0800 Received: from fnstmail02.fnst.cn.fujitsu.com (tang.cn.fujitsu.com [127.0.0.1]) by tang.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id r4M5Y0wg022008; Wed, 22 May 2013 13:34:03 +0800 Received: from G08FNSTD100614.fnst.cn.fujitsu.com ([10.167.233.156]) by fnstmail02.fnst.cn.fujitsu.com (Lotus Domino Release 8.5.3) with ESMTP id 2013052213324277-1422198 ; Wed, 22 May 2013 13:32:42 +0800 From: Hu Tao To: qemu-devel@nongnu.org Date: Wed, 22 May 2013 13:33:24 +0800 Message-Id: X-Mailer: git-send-email 1.8.2.3 In-Reply-To: References: X-MIMETrack: Itemize by SMTP Server on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/05/22 13:32:42, Serialize by Router on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/05/22 13:32:46, Serialize complete at 2013/05/22 13:32:46 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 222.73.24.84 Cc: Vasilis Liaskovitis , Jan Kiszka , Anthony Liguori , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Wanpeng Li Subject: [Qemu-devel] [RFC PATCH v1 20/20] q35-mch: move ram initialization into q35-mch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Hu Tao --- hw/i386/pc_q35.c | 7 ++----- hw/pci-host/q35.c | 36 +++++++++++++++++++++++++++++++----- include/hw/pci-host/q35.h | 9 +++++++-- 3 files changed, 40 insertions(+), 12 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a6d1eae..32c882e 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -65,7 +65,6 @@ static void pc_q35_init(QEMUMachineInitArgs *args) ISADevice *rtc_state; ISADevice *floppy; MemoryRegion *rom_memory; - MemoryRegion *ram_memory; GSIState *gsi_state; ISABus *isa_bus; int pci_enabled = 1; @@ -108,7 +107,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args) if (!xen_enabled()) { pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline, initrd_filename, below_4g_mem_size, above_4g_mem_size, - rom_memory, &ram_memory); + rom_memory); } /* irq lines */ @@ -121,11 +120,9 @@ static void pc_q35_init(QEMUMachineInitArgs *args) gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); } - q35_host->mch.ram_memory = ram_memory; + q35_host->mch.ram_size = ram_size; q35_host->mch.system_memory = get_system_memory(); q35_host->mch.address_space_io = get_system_io(); - q35_host->mch.below_4g_mem_size = below_4g_mem_size; - q35_host->mch.above_4g_mem_size = above_4g_mem_size; /* pci */ qdev_init_nofail(DEVICE(q35_host)); host_bus = q35_host->host.pci.bus; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index c57ab06..dddfc3c 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -243,24 +243,50 @@ static int mch_init(PCIDevice *d) { int i; hwaddr pci_hole64_size; + hwaddr below_4g_mem_size, above_4g_mem_size; MCHPCIState *mch = MCH_PCI_DEVICE(d); + if(mch->ram_size > MCH_PCI_HOLE) { + below_4g_mem_size = MCH_PCI_HOLE; + above_4g_mem_size = mch->ram_size - MCH_PCI_HOLE; + } else { + below_4g_mem_size = mch->ram_size; + above_4g_mem_size = 0; + } + + /* Allocate RAM. We allocate it as a single memory region and use + * aliases to address portions of it, mostly for backwards compatibility + * with older qemus that used qemu_ram_alloc(). + */ + memory_region_init_ram(&mch->ram, "pc.ram", + below_4g_mem_size + above_4g_mem_size); + vmstate_register_ram_global(&mch->ram); + memory_region_init_alias(&mch->ram_below_4g, "ram-below-4g", &mch->ram, + 0, below_4g_mem_size); + memory_region_add_subregion(mch->system_memory, 0, &mch->ram_below_4g); + if (above_4g_mem_size > 0) { + memory_region_init_alias(&mch->ram_above_4g, "ram-above-4g", &mch->ram, + below_4g_mem_size, above_4g_mem_size); + memory_region_add_subregion(mch->system_memory, MCH_PCI_HOLE_END, + &mch->ram_above_4g); + } + /* setup pci memory regions */ memory_region_init_alias(&mch->pci_hole, "pci-hole", mch->pci_address_space, - mch->below_4g_mem_size, - 0x100000000ULL - mch->below_4g_mem_size); - memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, + below_4g_mem_size, + 0x100000000ULL - below_4g_mem_size); + memory_region_add_subregion(mch->system_memory, below_4g_mem_size, &mch->pci_hole); pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : ((uint64_t)1 << 62)); memory_region_init_alias(&mch->pci_hole_64bit, "pci-hole64", mch->pci_address_space, - 0x100000000ULL + mch->above_4g_mem_size, + 0x100000000ULL + above_4g_mem_size, pci_hole64_size); if (pci_hole64_size) { memory_region_add_subregion(mch->system_memory, - 0x100000000ULL + mch->above_4g_mem_size, + 0x100000000ULL + above_4g_mem_size, &mch->pci_hole_64bit); } /* smram */ diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index 1c02420..1e985b4 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -53,8 +53,10 @@ typedef struct MCHPCIState { MemoryRegion pci_hole; MemoryRegion pci_hole_64bit; uint8_t smm_enabled; - ram_addr_t below_4g_mem_size; - ram_addr_t above_4g_mem_size; + ram_addr_t ram_size; + MemoryRegion ram; + MemoryRegion ram_below_4g; + MemoryRegion ram_above_4g; } MCHPCIState; typedef struct Q35PCIHost { @@ -147,4 +149,7 @@ typedef struct Q35PCIHost { #define MCH_PCIE_DEV 1 #define MCH_PCIE_FUNC 0 +#define MCH_PCI_HOLE 0xB0000000ULL +#define MCH_PCI_HOLE_END 0x100000000ULL + #endif /* HW_Q35_H */