From patchwork Tue Mar 17 04:43:58 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Grant Likely X-Patchwork-Id: 24540 X-Patchwork-Delegate: grant.likely@secretlab.ca Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 09E64DE29B for ; Tue, 17 Mar 2009 15:44:29 +1100 (EST) X-Original-To: linuxppc-dev@ozlabs.org Delivered-To: linuxppc-dev@ozlabs.org Received: from yx-out-2324.google.com (yx-out-2324.google.com [74.125.44.29]) by ozlabs.org (Postfix) with ESMTP id 15161DDF1C for ; Tue, 17 Mar 2009 15:44:00 +1100 (EST) Received: by yx-out-2324.google.com with SMTP id 8so1640074yxb.39 for ; Mon, 16 Mar 2009 21:43:58 -0700 (PDT) MIME-Version: 1.0 Received: by 10.151.41.21 with SMTP id t21mr9952935ybj.147.1237265038851; Mon, 16 Mar 2009 21:43:58 -0700 (PDT) In-Reply-To: References: <20090311222615.63410@gmx.net> <1237197925-71727-1-git-send-email-kosmo@semihalf.com> Date: Mon, 16 Mar 2009 22:43:58 -0600 Message-ID: Subject: Re: [PATCH] powerpc: Enable CPU_FTR_NEED_COHERENT for MPC52xx From: Grant Likely To: Piotr Ziecik Cc: LinuxPPC Mailing List , Kumar Gala X-BeenThere: linuxppc-dev@ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org On Mon, Mar 16, 2009 at 9:54 PM, Grant Likely wrote: > On Mon, Mar 16, 2009 at 4:05 AM, Piotr Ziecik wrote: >> BestComm, a DMA engine in MPC52xx SoC, requires snooping when >> CPU caches are enabled to work properly. >> >> Adding CPU_FTR_NEED_COHERENT fixes NFS problems on MPC52xx machines >> introduced by 'powerpc/mm: Fix handling of _PAGE_COHERENT in BAT setup code'. >>[...] >>  #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ >> -       || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) >> +       || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ >> +       || defined(CONFIG_PPC_MPC52xx) >>  #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT >>  #else >>  #define CPU_FTR_COMMON                  0 > > Aside from the fact that MPC10X_BRIDGE, PPC83xx and 8260 are already > doing it, adding the feature bit this way isn't multiplatform > friendly.  Essentially it means that all selected platforms will have > CPU_FTR_NEED_COHERENT enabled if CONFIG_PPC_MPC52xx is enabled. Here's my counter-patch. It contains the change to just G2_LE cores when MPC52xx is selected. However, this change will also affect some of the MPC82xx parts. However CPU_FTR_NEED_COHERENT shouldn't actually hurt anything, so maybe it would be better to just enable it unconditionally for the G2_LE core. Kumar/Ben, thoughts? g. diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cput index 4911104..48d7f5f 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -348,8 +348,15 @@ extern const char *powerpc_base_platform; CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) + +#if defined(CONFIG_PPC_MPC52xx) +#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ + CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NEED_COHERENT) +#else #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) +#endif + #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ CPU_FTR_COMMON)