From patchwork Tue May 21 06:39:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 245210 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4E2472C00AC for ; Tue, 21 May 2013 16:44:14 +1000 (EST) Received: from localhost ([::1]:39878 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegIu-0000oP-K4 for incoming@patchwork.ozlabs.org; Tue, 21 May 2013 02:44:12 -0400 Received: from eggs.gnu.org ([208.118.235.92]:53438) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegIY-0000ke-3a for qemu-devel@nongnu.org; Tue, 21 May 2013 02:43:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UegIW-0007a9-Oz for qemu-devel@nongnu.org; Tue, 21 May 2013 02:43:49 -0400 Received: from mail-pb0-x233.google.com ([2607:f8b0:400e:c01::233]:53675) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegIW-0007a5-FL for qemu-devel@nongnu.org; Tue, 21 May 2013 02:43:48 -0400 Received: by mail-pb0-f51.google.com with SMTP id jt11so298009pbb.24 for ; Mon, 20 May 2013 23:43:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=FP0r3GHbXUJpEnj+NKNYg2SvZhr7L5PGqKMNkZXPj1s=; b=PZw0GlNPfwUAOtu2lmZhlcobJx+BShfhpYfAiP8wu/nQ7Uu8/V/P9SlcIsjK27lX7B 7pMYUwefDpjQT2WPTTFcPmkX2Kflhb56QCHvHRes1QI9SKEvR6zwD+tdtXU+HVu880kg KpH1I6gZ7kT4BGSkAGKBx/+Ewu/zK5cYp+tdL59WQZTNsTRqQSBhUo9xfb6OFk6WqglT FRYUGgI0s1mrd7jTaDP2//61FAYpkQhx12zeUByPfemb1seG49Bre25VOD6OgoJpL+1f rA0KCq3CvkixLbZ7RFkrN18puYEt8d5rnzfsfB7nEIJaYEgfodebsVAH0uoHnp+aKA+C fvqQ== X-Received: by 10.68.219.70 with SMTP id pm6mr1146477pbc.154.1369118627603; Mon, 20 May 2013 23:43:47 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id 10sm1429290pbr.45.2013.05.20.23.43.44 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 20 May 2013 23:43:46 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Tue, 21 May 2013 16:39:28 +1000 Message-Id: <5ec47b13563ad2d22105a1f26186d7756718394b.1369117359.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.8.3.rc1.44.gb387c77.dirty In-Reply-To: References: X-Gm-Message-State: ALoCoQmD8ZEyHav4tNXEXDauT4Ex8xrpxe+KtHU9nsN2fSRLbipOI7bh0iow3HSGXgDRZzwYTfFk X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::233 Cc: edgar.iglesias@gmail.com Subject: [Qemu-devel] [PATCH arm-devs v4 15/15] xilinx_spips: lqspi: Fix byte/misaligned access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite The LQSPI bus attachment supports byte/halfword and misaligned accesses. Fixed. Refactored the LQSPI cache to be byte-wise instead of word wise accordingly. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- hw/ssi/xilinx_spips.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index e975a87..05a3ada 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -161,7 +161,7 @@ typedef struct { typedef struct { XilinxSPIPS parent_obj; - uint32_t lqspi_buf[LQSPI_CACHE_SIZE]; + uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; hwaddr lqspi_cached_addr; } XilinxQSPIPS; @@ -391,14 +391,12 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } } -static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max) +static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) { int i; - *value = 0; for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { - uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF; - *value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i); + value[i] = fifo8_pop(&s->rx_fifo); } } @@ -408,6 +406,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, XilinxSPIPS *s = opaque; uint32_t mask = ~0; uint32_t ret; + uint8_t rx_buf[4]; addr >>= 2; switch (addr) { @@ -437,7 +436,10 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, mask = 0; break; case R_RX_DATA: - rx_data_bytes(s, &ret, s->num_txrx_bytes); + memset(rx_buf, 0, sizeof(rx_buf)); + rx_data_bytes(s, rx_buf, s->num_txrx_bytes); + ret = s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_buf) + : cpu_to_le32(*(uint32_t *)rx_buf); DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); xilinx_spips_update_ixr(s); return ret; @@ -562,7 +564,8 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) if (addr >= q->lqspi_cached_addr && addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { - ret = q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2]; + uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; + ret = cpu_to_le32(*(uint32_t *)retp); DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, (unsigned)ret); return ret; @@ -608,13 +611,13 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) DB_PRINT_L(0, "starting QSPI data read\n"); - while (cache_entry < LQSPI_CACHE_SIZE / 4) { - for (i = 0; i < 16; ++i) { - tx_data_bytes(s, 0, 4); + while (cache_entry < LQSPI_CACHE_SIZE) { + for (i = 0; i < 64; ++i) { + tx_data_bytes(s, 0, 1); } xilinx_spips_flush_txfifo(s); - for (i = 0; i < 16; ++i) { - rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 4); + for (i = 0; i < 64; ++i) { + rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 1); } } @@ -622,7 +625,7 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) s->regs[R_LQSPI_STS] |= u_page_save; xilinx_spips_update_cs_lines(s); - q->lqspi_cached_addr = addr; + q->lqspi_cached_addr = flash_addr * num_effective_busses(s); return lqspi_read(opaque, addr, size); } } @@ -631,7 +634,7 @@ static const MemoryRegionOps lqspi_ops = { .read = lqspi_read, .endianness = DEVICE_NATIVE_ENDIAN, .valid = { - .min_access_size = 4, + .min_access_size = 1, .max_access_size = 4 } };